x energy savings. At the processor level, a run-time adaptive energy management scheme is employed that performs the following steps. a) Determine an Energy Minimizing Instruction Set: A tradeoff between leakage, dynamic, and reconfiguration energy is investigated and an energy-minimizing instruction set is selected for a dynamically reconfigurable processor under run-time varying performance a...

ÐWe illustrate the potential of techniques and results from the theory of network emulations to enhance the performance of a parallel architecture. The vehicle for this demonstration is a suite of algorithms that endow an N-processor bit-serial processor array A with a ameta-instructiono GAUGE k, which (logically) reconfigures A into an N=k-processor virtual machine Bk that has: 1) a datapath a...

The emerging need for large amounts of flexible computational power on embedded devices motivated many researchers to incorporate reconfigurable logic together with an instruction-set-processor (ISP) into their architectures. This implies that tomorrow’s applications will make use of both the ISP and the reconfigurable logic in order to provide the user with maximum performance. Today, however,...

The demand for 8-bit processors nowadays is still going strong despite efforts by manufacturers in producing higher end microcontroller solutions to the mass market. Low-end processor offers a simple, low-cost and fast solution especially on I/O applications development in embedded system. However, due to architectural constraint, complex calculation could not be performed efficiently on 8-bit ...

Nowadays, the datapaths of modem microprocessors reach their limits by using static instruction sets. A way out of these limitations is a dynamic reconfigurable processor datapath extension achieved by integrating traditional static datapaths with the coarse-grain dynamic reconfigurable XPParchitecture (eXtreme Processing Platform). Therefore, a loosely asynchronous coupling mechanism of the co...

Until a few years ago, processors were only sold as packaged individual ICs. The growing density of CMOS circuits, however, created an opportunity to incorporate the processor as part of a larger system on a chip. Initial processor designs for this market were based on the processor existing as a separate entity, and cores were handcrafted for each manufacturing process technology, resulting in...

Hybrid architectures, which are composed of a conventional processor closely coupled with reconfigurable logic, seem to combine the advantages of both types of hardware. They present some practical difficulties, however. The interface between the processor and the reconfigurable logic is crucial to performance and is often difficult to implement well. Partitioning the application between the pr...

Data security is in Demand in everyday life of Digital World, since Digital data’s can be reproduced much easily. To achieve the maximum security required a Parallel Processing, User Reconfigurable Cryptographic RISC Microprocessor is proposed in our paper. Rather than protecting the data using tools and external codes, a microprocessor is specially designed in our project to offer maximum digi...

Today, virtualization is often discussed on rather high abstraction levels (infrastructure, platform, software as a service). In contrast, in this talk the AMI-DAR processor concept [GH05] will be presented, which allows virtualization on the instruction set level as well as on the microarchitectural level. Running different instruction sets on the same hardware and microarchitecture is not a n...

This paper presents the design and implementation of the Discrete Fourier Transform@FT) algorithm on a reconfigurable processor system. While highly applicable to many engineering problems, the DFT is an extremely computationally intensive a * Consequently, the eventual goal of this work is to enhance the execution ofa floating-point precision DFT algorithm by off loading the algorithm from the...