In this paper, a low voltage dual-pulse-clock double edge triggered D'flip-flop (DPDET) is proposed. The DPDET flip-flop uses a split output latch clocked by a short pulse train. Compared to the previously reported double edge triggered flip-flops, the DPDET flip-flop uses only six transistors with two transistors being clocked, operating correctly under low supply voltage. The total transistor...

Efficient power management in wireless sensor network is a critical issue as the sensor nodes are low powered devices. In a sensor node, flip flop consumes large amount of power as they make maximum number of internal transitions. Reduction in the power consumed by flip-flops shows a deep impact on the total power consumed. Hence, designing low power flip flop cells are highly important for enh...

In this paper we present an ultra low-voltage and high speed D flip-flop. The flip-flop has an increased current level compared to standard CMOS circuits operating at low supply voltages. The increased current level is obtained by using a synchronized capacitive coupling to a semi floating-gate. The delay of the static differential flip-flop presented is less than 12% compared to conventional d...

In this paper, a novel low power pulsed flip-flop (PFF) using self-controllable pass transistor logic is presented. The pulse generation logic comprising of two transistor AND gate is used in the critical path of the design for improved speed and reduced complexity. In the D to Q path inverter is removed and the transistor is replaced with pass transistor logic. The pass transistor is driven by...

A new flip-flop design using a double-pulsed static latch is presented. The flip-flop has only a single stage of logic in the critical path and as a result is up to three times faster than the fastest previously known flip-flops, while consuming approximately the same energy as the lowestpower flip-flops. The flip-flop has asymmetric timing properties which make it a good match to skewed logic ...

The jitter, obtained by SFEMG recordings, mainly reflects the neuromuscular transmission time variability and is usually Gaussian distributed. Here is reported the bimodal distribution of the interpotential intervals, the flip-flop phenomenon. Long flip-flop in cases of reinnervation may indicate alternatively continuous and saltatory nerve conduction. Short flip-flop in normal subjects may be ...

In this paper, a high-speed double-edge-triggered flip-flop designed in 0.18μm CMOS technology is presented. Flip-flops, to a large extend, determine the speed of synchronous systems. The proposed flip-flop can operate with a clock rate as high as 12.5GHz, which translates to 25GB/s data rate. It samples the data on both edges of the clock. All signals are realized differentially. The different...

This paper describes a semi-dynamic CMOS flip-flop family featuring embedded Threshold Logic functions. First, we describe the new Threshold Logic flipflop concept and circuit operation. Second, we present the concepts of embedded Threshold logic and run-time reprogrammability. Finally, it is proved by Spice simulation results that wide (up to 8 inputs) AND/OR Boolean functions can be embedded ...

An all optical set-reset flip flop is presented that is based on two coupled identical laser diodes. The lasers are coupled so that when one of the lasers lases it quenches lasing in the other laser. The state of the flip flop is determined by which laser is currently lasing. Rate equations are used to model the flip flop and obtain steady state characteristics. The flip flop is experimentally ...