A novel foaming process-chemical foaming process (CFP)-using foaming agents to fabricate wafer-level micro glass cavities including channels and bubbles was investigated. The process consists of the following steps sequentially: (1) shallow cavities were fabricated by a wet etching on a silicon wafer; (2) powders of a proper foaming agent were placed in a silicon cavity, named 'mother cavity', ...

This paper presents one wafer level packaging approach of quartz resonator based on through-silicon via (TSV) interposer with metal or polymer bonding sealing of frequency components. The proposed silicon-based package of quartz resonator adopts several three-dimensional (3D) core technologies, such as Cu TSVs, sealing bonding, and wafer thinning. It is different from conventional quartz resona...

During the last decades it has been shown that non-contact AFM can be used as an efficient lithographic technique capable of manufacturing nanometer sized devices on the surface of a silicon wafer. The AFM nanooxidation approach is based on generating a potential difference between a cantilever needle tip and a silicon wafer. A water meniscus builds up between the tip and the wafer, resulting i...

A novel heating technique, electromagnetic induction heating (EMIH), uses electromagnetic radiation, ranging in frequency from a few megahertz to tens of gigahertz, to volumetrically heat silicon above 1000 C in only a few seconds. Typical power requirements fall between 900 to 1300 W for silicon wafers 75 to 100 mm in diameter. This technique has successfully produced direct silicon wafer-to-w...

This paper discusses sputtered silicon encapsulation as a wafer level packaging approach for isolatable MEMS devices. Devices such as accelerometers, RF switches, inductors, and filters that do not require interaction with the surroundings to function, could thus be fully encapsulated at the wafer level after fabrication. A MEMSTech 50g capacitive accelerometer was used to demonstrate a sputter...

Getting Micro-Electro-Mechanical Systems (MEMS) out of a wafer after fabrication processes is of great interest in testing, packaging or simply using these devices. Actual solutions require special machines like wafer dicing machines, increasing time and cost of de-tethering MEMS. This article deals with a new solution for manufacturing mechanical de-tetherable silicon MEMS. The presented solut...

We have developed a one-step, hydrofluoric acid-free hydrothermal etching method that not only produces bismuth nano/micrometer-sized spheres but also prepares porous silicon with vertical holes. By controlling the heating temperature and time, nanoscale vertical-channeled porous silicon can be received. Our result indicated that the Bi clusters were formed first on the wafer surface. Then the ...

Silicon direct bonding (SDB) is a bonding technique of two silicon wafers together with homogeneous or heterogeneous layers without the use of any intermediate adhesives. The SDB technique simplifies the process and cost by reducing mask level, and its necessity has increased in terms of its fields of applications such as power devices, SOI, sensors and actuators. Factors which can affect direc...

This paper introduces a photoluminescence-based technique for determining the acceptor concentration in silicon wafers by measuring the formation rate of iron-acceptor pairs. This rate is monitored by bandto-band photoluminescence in low injection, the intensity of which is proportional to the carrier lifetime. The technique is demonstrated with an iron-implanted float zone silicon wafer, heavi...

silicon nanowire (sinw) arrays were produced by electroless method on polycrystalline si substrate, in hf/ agno3 solution. although the monocrystalline silicon wafer is commonly utilized as a perfect substrate, polycrystalline silicon as a low cost substrate was used in this work for photovoltaic applications. in order to study the influence of etching time (which affects the sinws length) on d...