Cascode CMOS op-amps use a large number of external bias voltages. This results in numerous drawbacks, namely, an area and power overhead, susceptiblity of the bias lines to noise and cross-talk and high sensitivity of the bias point to process variations. In this paper we present a self-biasing technique for folded cascode CMOS op-amps that uses no additional devices and no baas voltages other...

A Low Noise Amplifier (LNA) is an important building block in the RF receiver chain. Typically the LNA should provide acceptable gain and high linearity while maintaining low noise and power consumption. To optimize these conflicting goals the so-called Cascode topology is widely used in industry. Here the gain cell is comprised of two transistors, one in common-source and the other in common g...

This paper presents an optimized methodology to folded cascode operational transconductance amplifier (OTA) design. The design is done in different regions of operation, weak inversion, strong inversion and moderate inversion using the gm/ID methodology in order to optimize MOS transistor sizing. Using 0.35μm CMOS process, the designed folded cascode OTA achieves a DC gain of 77.5dB and a unity...

In recent years, there has been an increasing demand for high-speed digital circuits at low power consumption. This paper presents a design of input stage of Operational Amplifier i.e cascode differential amplifier using a standard 65nm CMOS Technology.A comparison betweem gate-driven, bulk-driven and cascode bulk driven bulk-driven differential amplifier is described. The Results demonstrate t...

A body-biasing compensation scheme based on two proportional-toabsolute-temperature (PTAT) circuits is proposed to reduce the PVT variability of the DC gain of cascode amplifiers. A brief description of a basic PTAT is given as well as its application to cascode-based operational transconductance amplifiers. Simulation results show that the proposed compensated circuit amplifier exhibit a (DC) ...

This paper addresses the issues involved in designing 1V Op-amp in standard digital CMOS technology. Bulk-driving technique is used to circumvent the metal–oxide semiconductor field-effect transistor turn-on (threshold) voltage requirement. The Op-amp will be designed in a Europractice 0.7μm n-well CMOS process having threshold voltage of 0.76V and –1V for NMOS and PMOS respectively. Simple and...