This paper presents an advanced hardware architecture for integer transform, quantization, inverse quantization and inverse integer transform modules dedicated to the macroblock engine of the H.264/AVC video codec standard. Our highly parallel and pipelined architecture is designed to be used for intra and inter prediction modes in H.264/AVC. The TQ/IQT design is described in VHDL language and ...

This paper presents low-cost, configurable PCI Express (PCIe) direct memory access (DMA) interface for implementation on Intel Cyclone V FPGAs. The DMA engine was designed to support DAQ tasks including continuous pretriggering acquisition transient analysis and multichannel transmission. Proposed solution is based SoPC resources. Performance of the has been evaluated Terasic OVSK board (PCIe G...

A novel k-winners-take-all (k-WTA) competitive learning (CL) hardware architecture is presented for on-chip learning in this paper. The architecture is based on an efficient pipeline allowing k-WTA competition processes associated with different training vectors to be performed concurrently. The pipeline architecture employs a novel codeword swapping scheme so that neurons failing the competiti...

This paper describes prototyping of a neuroadaptive smart antenna beamforming algorithm using hardware-software implemented RBF neural network and FPGA system-on-programmable-chip (SoPC) approach. The aim is to implement the adaptive beamforming unit in a combination of hardware and software by estimating its performance against the fixed real-time constraint based on IMT-2000 family of 3G cell...

Our project implements a software-defined radio (SDR) in a Nios® II processor. A software-defined radio is a radio that provides software control of a variety of modulation and demodulation techniques, wide-band or narrow-band operation, communications security functions (such as hopping), and waveform requirements of current and evolving standards over a broad frequency range. In this project,...

Embedding a System on a Programmable Chip with in the constraint of available resources brings out ingenuity of a SoPC designer. The paper covers an efficient Soft processor based USB communication device driver implementation on FPGA using a 10% foot print so as to set aside the rest 90% of the logic resources of the programmable chip for other compute and control intensive tasks. Using a Soft...

Previous research shows that there are two architectures for speechto-speech translation (S2ST) system implementation. One is client-server based systems that should be built on the server computer but not available anytime or anywhere. The other is to build portable stand-alone devices but lacks the real-time performance. Therefore, this work presents an embedded system design for portable S2S...

The efficient solution of large systems of linear equations represented by sparse matrices appears in many tasks. LU factorization followed by backward and forward substitutions is widely used for this purpose. Parallel implementations of this computation-intensive process are limited primarily to supercomputers. New generations of Field-Programmable Gate Array (FPGA) technologies enable the im...

as functional integration has increased in hand-held consumer devices features such as global positioning system (gps) receivers have been embedded in increasingly more devices in recent years. for example, the train positioning system based on gps provides an integrated positioning solution which can be used in many rail applications without a cost intensive infrastructure. the network built i...

The Network-on-chip (NoC) designs consisting of large pack of Intellectual Property (IP) blocks (cores) on the same silicon die is becoming technically possible nowadays. But, the communication between the IP Cores is the main issue in recent years. This paper presents the design of a Code Division Multiple Access (CDMA) based wrapper interconnect as a component of System on programmable chip (...