The placement of substrate contacts in epi and non-epi technologies is analyzed in order to control and reduce the substrate noise amplitude and spreading. The choice of small or large substrate contacts or rings for each of the two major technologies is highlighted. Design guidelines for placing substrate contacts so as to improve the noise immunity of digital circuits in mixed-signal smart-po...

Existing research in substrate coupling noise in mixedsignal circuits has concen tratedon the problem of the high speed digital circuitry in uencing the highly sensitive analog circuitry [1{6]. It has been demonstrated in the literature that physical design plays an important role in minimizing the in uence of substrate noise generated by the digital circuitry, a ecting the highly sensitive ana...

This paper identifies the physical origin and contribution mechanism of substrate induced channel thermal noise in MOSFETs. Resistance of the substrate generates potential fluctuations that in turn produce additive channel noise via the channel depletion capacitor. The additive noise may result in a frequency dependence of the drain current noise due to a pole associated with the Rsub-Cdepl net...

The mixed-signal circuits with both analog and digital blocks on a single chip have wide applications in communication and RF circuits. Integrating these two blocks can cause serious problems especially in applications requiring fast digital circuits and high performance analog blocks. Fast switching in digital blocks generates a noise which can be introduced to analog circuits by the common su...

The coupling of simultaneous switching noise through the substrate presents an important issue to integration of both noisy digital and sensitive analog circuitry in mixedsignal integrated circuits. Noise is generated by digital aggressor circuits, it further propagates through the common substrate, and finally impacts the performance of analog victim circuitry through body effect and capacitiv...

Through-Silicon Via (TSV) is a critical interconnect element in 3D integration technology. TSVs introduce many new design challenges. In addition to competing with devices for real estate, TSVs can act as a major noise source throughout the substrate. We present in this paper a comprehensive study of TSV-induced noise as a function of several critical design and process parameters including sub...

Charge noise is critical in the performance of gate-controlled quantum dots (QDs). Such information is not yet available for QDs made out of the new material graphene, where both substrate and edge states are known to have important effects. Here we show the 1/f noise for a microscopic graphene QD is substantially larger than that for a macroscopic graphene field-effect transistor (FET), increa...

This paper presents a methodology to simulate, at the system level, the substrate noise coupling to phase locked loop (PLL) circuits in mixed signal systems. Macro-modeling for digital noise injection and propagation through the substrate are considered. Behavioral models of the PLL for noise sensing as well as intrinsic functionality are abstracted from transistor level circuit analysis result...