We determine which (ordinary) Riordan arrays are the coefficient arrays of a family of orthogonal polynomials. In so doing, we are led to introduce a family of polynomials, which includes the Boubaker polynomials, and a scaled version of the Chebyshev polynomials, using the techniques of Riordan arrays. We classify these polynomials in terms of the Chebyshev polynomials of the first and second ...

We develop new algorithms and architectures for matrix multiplication on configurable hardware. These designs significantly reduce the latency as well as the area. Our designs improve the previous designs in [7] and [1] in terms of the area/speed metric where the speed denotes the maximum achievable running frequency. The area/speed metrics for the designs in [7], [1], and our design are 14.45,...

To solve linear state equations, a twodimensional systolic-array system has been proposed [SI. For the same purpose, various kinds of one-dimensional arrays are designed in the paper. The linear systolic-array system with first-in-firstout (FIFO) queues can be designed by applying double projections from the three-dimensional dependence graph (DG). As the array thus designed needs processors wi...

This report introduces a new systolic algorithm for the sequence alignment problem. This work builds upon an existing systolic array for computing the edit distance between two sequences. The alignment array is meant to be used as the second phase in a two-phase design with a modiied edit distance array serving as the rst phase. An implementation on the SPLASH programmable logic array is descri...

The QR decomposition, recursive least squares (QRD RLS) algorithm is one of the most promising RLS algorithms, due to its robust numerical stability and suitability for VLSI implementation based on a systolic array architecture. Up to now, among many techniques to implement the QR decomposition, only the Givens rotation and modified GramSchmidt methods have been successfully applied to the deve...

We first relate the architecture of systolic arrays to the technological and economic design forces acting on architects of special-purpose systems some 20 years ago. We then observe that those same design forces now are bearing down on the architects of contemporary general-purpose processors, who consequently are producing general-purpose processors whose architectural features are increasing...