A dense and fast threshold-logic gate with a very high fan-in capacity is described. The gate performs sum-ofproduct and thresholding operations in an architecture comprising a poly-to-poly capacitor array and an inverter chain. The Boolean function performed by the gate is soft programmable. This is accomplished by adjusting the threshold with a dc voltage. Essentially, the operation is dynami...

This paper presents a face recognition method implemented using reconfigurable network of memristive threshold logic cells that can be practically realised in a secondary plane to the pixel arrays. Among the most distinguishing features of the presented system are a) an early detection and storage of only the relevant information directly from the sensors, b) a parallel, scalable information st...

We introduce a new dual threshold voltage technique for domino logic. Since domino logic is much more sensitive to noise, noise margins have to be taken into account when applying dual threshold voltages to domino logic. To guarantee the signal integrity in domino logic, we carefully consider the effect of transistor sizing and threshold voltage selection. For optimal design, tradeoffs need to ...

In this paper we propose a high-speed hybrid ThresholdBoolean logic style suitable for Boolean symmetric functions implementation. First, we present a depth-2 hybrid implementation scheme for arbitrary symmetric Boolean functions, based on differential Threshold logic gates as circuit style. Finally, we present the hybrid logic design of a counter. The simulation results, suggest that the hybri...

After a short review of the state-of-the-art, a new low-power differential threshold logic gate is introduced: split-precharge differential noiseimmune threshold logic (SPD-NTL). It is based on combining the split-level precharge differential logic, with a technique for enhancing the noise immunity of threshold logic gates: noise suppression logic. Another idea included in the design of the SPD...