AbstructA direct approach to transistor sizing for minimizing the power consumption of a CMOS circuit under a delay constraint is presented. In contrast to the existing assumption that the power consumption of a static CMOS circuit is proportional to the active area of the circuit, it is shown that the power consumption is a convex function of the active area. Analytical formulation for the pow...

In this article a low power and low latency 4-2 compressor has been presented. By using modified truth table and Pass Transistor Logic (PTL) a novel structure has been proposed which outperforms previous designs from the frequency of operation view point. The proposed design method has reduced the total transistor count considerably which will lead to reduced power consumption and smaller activ...

Model Timo Veijola, Mikael Andersson*, and Antti Kallio Helsinki University of Technology, Faculty of Electrical Engineering, Circuit Theory Laboratory, Otakaari 5A, FIN-02150 Espoo, Finland. phone:+358-0-4512293, fax:+358-0-460224, e-mail:[email protected] *Nokia Research Center. P.O. Box 45, FIN-00211 Helsinki, Finland. Abstract| A simple method for transistor DC parameter extraction is prese...

A new bipolar transistor model called VBIC has recently been developed and is likely to replace the Gummel–Poon model as the new industry standard bipolar transistor model. This paper focuses on the comparison of the VBIC and Gummel–Poon models under the dc operations. The extraction and optimization procedure coded in S+ statistical language and required for VBIC simulation is also developed a...