We previously proposed the circular defect in two-dimensional photonic crystal (CirD) laser based on a GaAs/AlGaAs multilayer wafer, which is fabricated by dry etching. This CirD uses InAs quantum dot (QD) layers as gain medium, but this inhibits vertical improved etching process introducing three QD and three-step for fabricating laser. As result, structures with good profiles could be excelle...

Anisotropic wet etching is a most widely employed for the fabrication of MEMS/NEMS structures using silicon bulk micromachining. The use of Si{110} in MEMS is inevitable when a microstructure with vertical sidewall is to be fabricated using wet anisotropic etching. In most commonly employed etchants (i.e. TMAH and KOH), potassium hydroxide (KOH) exhibits higher etch rate and provides improved a...

A quantitative model capturing pattern dependent effects and time evolution of the etch rate in Deep Reactive Ion Etching (DRIE) is presented. DRIE is a key process for pattern formation in semiconductor fabrication. Non-uniformities are caused due to microloading and aspect ratio dependencies. The etch rate varies over time and lateral etch consumes some of the etching species. This thesis con...

Some of the key components are demonstrated to make three-dimensional (3-D) optical integrated circuits possible using polymers. Fabrication techniques of shadow reactive ion etching, shadow photolithography, and gray-level photolithography to produce complex 3-D integrated optic structures are demonstrated. Vertical waveguide bends exhibit excess losses of <0.3 dB, and vertical power splitters...

A 1500mm 1200 mm silicon scanning mirror for laser display has been designed and fabricated by deep inductively coupled plasma reactive ion etching (ICPRIE) and flip chip bonding technology. It is a vertically driven electrostatic scanner and composed of two structures having vertical comb fingers. The upper structure is composed of a scanning mirror plate, two torsion bars, a supporting frame ...

A simple method for fabricating vertically stacked single-crystal silicon nanowires on standard bulk silicon wafers is presented. The process uses inductively coupled plasma (ICP) etching to create silicon fins with uneven yet controllable vertical profiles. The fins are then thermally oxidized in a self-limiting process, and the narrow regions are completely consumed to create multiple nanowir...

Towards the demonstration of sub-10 nm III-V vertical fin and nanowire MOSFETs, a novel alcohol-based digital-etch technology has been developed. The new technique minimizes the mechanical forces exerted on vertical nanowire structures. A consistent 1 nm/cycle etching rate on both InGaAs and InGaSb-based heterostructures has been obtained. This is the first demonstration of digital etch on anti...

P-type and N-type multi-gate vertical thin film transistors (vertical TFTs) have been fabricated, adopting the low-temperature (T ≤ 600°C) polycrystalline silicon (polysilicon) technology. Stacked heavily-doped polysilicon source and drain are electrically isolated by an insulating barrier. Multi-teeth configuration is defined by reactive ion etching leading to sidewalls formation on which undo...