Architecture and Compiler Support for a VLIW Execution Model on a Coarse-Grained Reconfigurable Array

This paper presents an architecture that combines VLIW (very long instruction word) processing with the capability to introduce application-specific customized instructions and highly parallel combinational hardware functions for the acceleration of signal processing applications. To support this architecture, a compilation and design automation flow is described for algorithms written in C. Th...

compiler to exploit high ILP using EPIC techniques [SI. M-64 processor architecture implementing this concept is the processor architecture where the compiler is responsible for This paper evaluates performance of the Dynamically efficiently exploiting the available ILP and keeps the Inslructian Sch&led KlW P I S w pmcersor mhitechnz. executions busy. Instead of the merits, the IA-64 processor ...

instruction format design, template design, instruction-set architecture, abstract ISA, concrete ISA, VLIW processors, EPIC processors, HPL-PD architecture, instruction encoding, bit allocation, affinity allocation, applicationspecific processors, design space exploration Very long instruction word (VLIW), and in its generalization, explicitly parallel instruction computing (EPIC) architectures...

The Dynamically Instruction Scheduled VLIW (DISVLIW) processor architecture is designed for balancing scheduling effort more evenly between the compiler and the processor. The DISVLIW instruction format is augmented to allow dependency bit vectors to be placed in the same VLIW word. Dependency bit vectors are added to each instruction format within long instructions to enable synchronization be...

Digital signal processors with Harvard architecture are being gradually replaced by digital signal processors with VLIW (Very Long Instruction Word) architecture for high-end applications. Owing to exploiting the principles of parallel instruction processing and parallel data processing, the new architecture provides the calculation power to implement complex algorithms of digital signal proces...

Recent families of Digital Signal Processors show a VLIW-like architecture. These processors comprise of multiple execution units agglomerated into several data paths. With heavily pipelined, atomic RISC like operations, these are able to execute several instructions in a single cycle. The scheduling is done statically, and this saves hardware at the expense of more sophisticated compiler. This...

Clustered VLIW embedded processors have become widespread due to benefits of simple hardware and low power. However, while some applications exhibit large amounts of instruction level parallelism (ILP) and benefit from very wide machines, others have little ILP, which wastes precious resources in wide processors. Simultaneous MultiThreading (SMT) is a well known technique that improves resource...

This paper presents dual-thread Weld architecture for VLIW/EPIC processors. The dual-thread Weld model supports one main thread and one speculative thread running simultaneously in a VLIW/EPIC processor with a register file and a fetch unit per thread. This paper analyzes the cost-performance impact of the dual-thread Weld model, which includes analysis of migrating the disambiguation hardware ...