High-performance PMOSFETs with sub-50–nm gate-length are reported. A self-aligned double-gate MOSFET structure (FinFET) is used to suppress the short-channel effects. This vertical double-gate SOI MOSFET features: 1) a transistor channel which is formed on the vertical surfaces of an ultrathin Si fin and controlled by gate electrodes formed on both sides of the fin; 2) two gates which are self-...

In this paper, we analyze the variability of III-V homojunction tunnel FET (TFET) and FinFET devices and 32-bit carry-lookahead adder (CLA) circuit operating in near-threshold region. The impacts of the most severe intrinsic device variations including work function variation (WFV) and fin line-edge roughness (fin LER) on TFET and FinFET device Ion, Ioff, Cg, 32-bit CLA delay and power-delay pr...

FinFET has appeared to be a good candidate for further extending the technology to the nanoscale regime due to its excellent electrostatic properties and comparative ease of fabrication. Due to little/no body effect in FinFET devices, there is a good chance of increasing the stack height to enable more complex gates and reduce logic depth, which could further improve metrics, like performance. ...

Considering the difficulties in planar CMOS transistor scaling to secure an acceptable gate to channel control FinFET based multi-gate (MuGFET) devices have been proposed as a technology option for replacing the existing technology. The desirability of FinFET that it’s operation principle is same as CMOS process. This permits to lengthening the gate scaling beyond the planar transistor limits, ...

Conventional CMOS technology's performance deteriorates due to increased short channel effects. Double-gate (DG) FinFETs has better short channel effects performance compared to the conventional CMOS and stimulates technology scaling. The main drawback of using CMOS transistors are high power consumption and high leakage current. Fin-type field-effect transistors (FinFETs) are promising substit...

Abstract: We present the optimization of the manufacturing process of the 5nm bulk-FinFET technology by using the 3D process and device simulations. In this paper, bysimulating the manufacturing processes, we focus on optimizing the manufacturingprocess to improve the drive current of the 5nm FinFET. The improvement of drivecurrent is one of the most important issues in ...

According to the Moore’s Law, the number of transistors in a unit chip area double every two years. But the existing technology of integrated circuit formation is posing limitations to this law. CMOS technology shows certain limitations as the device is reduced more and more in the nanometer regime out of which power dissipation is an important issue. FinFET is evolving to be a promising techno...

As technology has scaled down, the implications of leakage current and power analysis for memory design have increased. To minimize the short channel effect Double-gate FinFET can be used in place of conventional MOSFET circuits due to the self-alignment of the two gates. Design for XOR and XNOR circuits is suggested to improve the speed and power. These circuits act as basic building blocks fo...

This paper describes the design of a bandgap reference, implemented in 32 nm FinFET technology. The paper introduced new method for increasing stability of output voltage of bandgap circuit. In the proposed architecture extra feedback is used for setting the output voltage in fixed voltage. This feedback makesbandgap circuit more stable and speedy employing back gate biasing of the FinFET devic...