Scalability poses a severe threat to the existing DRAM technology. The capacitors that are used for storing and sensing charge in DRAM are generally not scaled beyond 42nm. This is because; the capacitors must be sufficiently large for reliable sensing and charge storage mechanism. This leaves DRAM memory scaling in jeopardy, as charge sensing and storage mechanisms become extremely difficult. ...

Abstract In this study, we developed a capacitorless dynamic random-access memory (DRAM) (1T-DRAM) device based on junctionless (JL) bulk-fin field-effect transistor structure with excellent reliability and negligible variability against work-function variation (WFV). We investigated the in transfer characteristics performance of cell owing to WFV. particular, investigate WFV effect, analyzed 2...

ÐThis paper presents a simulation-based performance study of several of the new high-performance DRAM architectures, each evaluated in a small system organization. These small-system organizations correspond to workstation-class computers and use only a handful of DRAM chips (~10, as opposed to ~1 or ~100). The study covers Fast Page Mode, Extended Data Out, Synchronous, Enhanced Synchronous, D...

The aim of this study was to investigate the effects of the adenoviral-mediated autophagy gene, damage-regulated autophagy regulator (DRAM), on the proliferation and autophagy of SGC7901 human gastric cancer cells in vitro. The recombinant adenovirus, AdMax-pDC315-DRAM-EGFP, working as a virus vector of DRAM was constructed and infected into the SGC7901 human gastric cancer cell line. The MTT a...

Commodity DRAM-based processing-using-memory (PuM) techniques that are supported by off-the-shelf DRAM chips present an opportunity for alleviating the data movement bottleneck at low cost. However, system integration of these imposes non-trivial challenges yet to be solve d . Potential solutions require appropriate tools develop any necessary hardware and software components. Unfortunately, cu...

A microprocessor integrated with DRAM on the same die has the potential to improve system performance by reducing memory latency and improving memory bandwidth. In this paper we evaluate the performance of a single chip multiprocessor integrated with DRAM when the DRAM is organized as on-chip main memory and as on-chip cache. We compare the performance of this architecture with that of a more c...

This paper shows how to run multithreaded programs on a DRAM (Distributed Random Access Memory) parallel computer and demonstrates that such programs can run efficiently on a collection of machines distributed across thousands of miles over the internet. Suppose we have a fully strict multithreaded program has work and critical-path length , and we have a processor DRAM machine with an upper bo...

Productive HIV infection of CD4(+) T cells leads to a caspase-independent cell death pathway associated with lysosomal membrane permeabilization (LMP) and cathepsin release, resulting in mitochondrial outer membrane permeabilization (MOMP). Herein, we demonstrate that HIV infection induces damage-regulated autophagy modulator (DRAM) expression in a p53-dependent manner. Knocking down the expres...