This paper reports the implementation and performance evaluation of the OpenSHMEM 1.3 specification for the Adapteva Epiphany architecture within the Parallella single-board computer. The Epiphany architecture exhibits massive many-core scalability with a physically compact 2D array of RISC CPU cores and a fast network-on-chip (NoC). While fully capable of MPMD execution, the physical topology ...

The Adapteva Epiphany MIMD architecture is a scalable, two-dimensional (2D) array of RISC cores with minimal uncore functionality connected with a fast 2D mesh network on a chip (NoC). We apply a threaded MPI programming model for image processing kernels including a 2D Fast Fourier Transform (FFT) with high-pass filter for edge detection; local operators for Gaussian image smoothing; and a Sob...

Alike interconnection networks for parallel systems, Networks-onchip (NoC) must provide high bandwidth and low latency, but they are further constrained by their on-chip power budget. Consequently, simple network topologies such as the 2D Mesh with shallow buffers and simple routing strategies such as dimensional order routing (DOR) have been widely used in order to achieve this goal. A low num...

The use of rapid prototyping tools such as MATLAB-Simulink and VHDL-Modelsim becomes progressively more essential for system-on-chip (SoC) design verification because of time-to-market constraints. This paper presents a Modelsim/MATLAB Co-simulation for image processing in multi-core systems (MCSoC) with QoS requirements. The methodology aims to improve the design verification efficiency for im...

Clos Network on Chip (CNOC) is a promising Network on Chip (NOC) topology because of its low hop counts and good load-balancing characteristics. The throughput of a CNOC depends on the specific router design, which includes at least two major components: buffering structure and switching allocation (SA). In this paper, we propose three cut-through SA schemes for Virtual Output Queue (VOQ)-based...

Now days, as per the recent studies, the development of integration technology, System on-Chip (SoC), has large number of transistor. NoC has been proposed as a highly structured and scalable solution to address communication problems in SoC. As the microprocessor industry is moving from single-core to multicore architectures, which require efficient communications processors. Also both SoC and...

System on Chip (SoC) design in the billion transistor era will involve the integration of numerous heterogeneous semiconductor intellectual property blocks. Some of the main problems arise from non-scalable global wires delays, failure to achieve global synchronization and errors due to signal integrity issues. In order to keep a low time-to-market factor new design methodologies must be develo...

With the feature size of semiconductor technology reducing and intellectual properties (IP) cores increasing, on chip communication architectures have a great influence on the performance and area of System-on-Chip(SoC) design. Network-on-Chip(NoC) has been proposed as a promising solution to complex SoC communication problems and has been widely accepted by academe and industry. Focusing on de...

Network-on-chip (NoC) is deemed to be a paradigm to tackle design challenges in the billion transistor era. A NoC provides a reusable platform for integrating heterogeneous resources. This report discusses application design on NoC. We propose Network-on-Chip Assembler Language (NoC-AL) that serves an interface between NoC implementations and applications, very similar to the instruction set of...

In this paper, a Clustered NOC (C-NOC) is introduced to improve the performance of Hermes-NOC (H-NOC) in group communication. Each C-NOC switch has eight bi-directional ports connected to four neighbor switches and four local ports. With the same (IP) cores in both H-NOC and C-NOC networks, the ordinal size of C-NOC is 75% less than H-NOC. In corner-to-corner communication, C-NOC operates 29% f...