In this paper we describe an efficient implementation of the Tate and Ate pairings using Barreto-Naehrig pairing-friendly curves, on both a standard PC and on a 32-bit smartcard. First we introduce a subfamily of such curves with a particularly simple representation. Next we consider the issues that arise in the efficient implemention of field arithmetic in Fp12 , which is crucial to good perfo...

Multipliers are one of the most important building blocks in processors. This paper describes a low-power 32×32-bit parallel multiplier, designed and fabricated using a 0.13 μm double-metal doublepoly CMOS process. In order to achieve low-power operation, the multiplier was designed utilizing mainly pass-transistor logic circuits, without significantly compromising the speed performance of the ...

−This paper presents the design, fabrication and characterization of a 32 by 32 electroplated micromirror array on a glass, a low cost substrate. Approaches taken in this work for the fabrication of micromachined mirror arrays include a line addressing scheme, a seamless array design for high fill factor, planarization techniques of polymeric interlayers, a high yield methodology for the remova...