This paper presents an all-digital phase-locked loop (PLL) using a voltage-domain digitization realized by an analog-to-digital converter (ADC). It consists of an 18b Class-C digitally-controlled oscillator (DCO), 4b comparator, digital loop filter (DLF), and frequency-locked loop (FLL). Implemented in 65nm CMOS technology, the proposed PLL reaches an in-band phase noise of -112dBc/Hz and an RM...

Addition is the fundamental operation for any VLSI processors or digital signal processing. In this paper focuses on carry -look ahead adders have done research on the design of high-speed, low-area, or low-power adders. Here domino logic is used for implementation and simulation of 128 bit Carrylook ahead adder based HSPICE Tool. In adder circuits propagation delay is the main drawback. To ove...

This work consists in a dynamic voltage scaling methodology, with Fault-Tolerance capability, to be used during circuits’ lifetime operation. Methodology implements on-line circuit monitoring, restricting power consumption by adjusting dynamically the power-supply voltage to the minimum value that prevent errors. Error free operation is achieved by using a cooperative work of global and local s...

A 65-GHz Class-C LC oscillator designed in 65nm CMOS technology by ST Microelectronics is presented. A three spiral transformer has been used to achieve low phase noise and low power consumption. Post-layout simulations show a phase noise is equal to -88.4 dBc/Hz at 1-MHz offset from the carrier (65.8 GHz). The power consumption is 14 mW with 1.2-V supply voltage. The oscillator is capable to o...

With the continuously growing quest for miniaturization of circuit technology, one of the prime focuses of the research has shifted in the direction of ultra low power circuit designs. As the size of chips is shrinking and the density is increasing simultaneously, losses are increasing mostly in the form of power dissipation. Based on various parameters of performance evaluation in a VLSI circu...

A down conversion RF mixer is designed with 65nm CMOS technology for a different low power consumption applications. Mixer structure comprises a double-balanced Gilbert-Cell with improving linearity method in the RF stage of circuit; all is at a supply voltage of 1.8V and a power of 2.17 mW. The circuit is simulated for different spectrum applications as: 200 MHz mobile users, 1.9 GHz wireless ...

For huge systems like video processing, FPGA prototyping plays an important role before taping out. In this paper, a verification system for H.264/AVC encoders with FPGA prototyping is proposed and implemented. An H.264 encoder with baseline profile of Level 3.2 was carried out with a clock frequency of 200MHz on a Xilinx Virtex-6 FPGA connected with DDR3 memory, which could satisfy real-time e...

Energy-efficient conversion of DC voltages is gaining more and more importance in low-power applications, especially in mobile and wireless systems. Several control techniques can be applied to achieve output regulation of a Buck DC-DC converter. In this paper a linear PID (proportional-integral-derivative) control loop, both in analog and digital domain, is derived and its performance is compa...

As the CMOS technology is scaling down, leakage power has become one of the most critical design concerns for the chip designer. This paper proposes a low leakage linear feedback shift register that can be used in a crypto-processor. In this work, three bit, four bit and five bit linear feedback shift registers are implemented in 90nm and 65nm technology . This paper also proposes two leakage r...

An accurate analytical transient response and propagation delay model of nano CMOS inverter is presented. A modified version of α -power law MOSFET current model is proposed. The proposed model overcomes the over-estimation of linear region current in α -power law current model, and takes into account the channel length modulation effects in nano devices. A new methodology to estimate propagati...