Acknowledgement It has been a real privilege and honor to be a graduate student in joint master program of micro-electronic department at Fudan University and SoC program of Royal Institute of Technology (KTH). It is definitely an enjoyable and unforgettable experience to work with many brilliant students and teachers across country borders. I am deeply indebted to many people who have assisted...

A novel three-phase phase-locked loop solution is proposed based on D-Q transformation aiming at the AC-DC rectifier with high efficiency and high power factor. The phase-locked loop is implemented digitally using the Xilinx blockset integrated with Matlab/Simulink. The three-phase digital phase-locked loop (TDPLL) is elaborately designed with the parameters defined in detail. The AC-DC convert...

An efficient architecture for low jitter All Digital Phase Locked Loop (ADPLL) suitable for high speed SoC applications is presented in this paper. The ADPLL is designed using standard cells and described by Hardware Description Language (HDL). The ADPLL implemented in a 90 nm CMOS process can operate from 10 to 200 MHz and achieve worst case frequency acquisition in 14 reference clock cycles. ...

This paper deals with performance analysis and implementation of a three phase inverter fed induction motor (IM) drive system. The closed loop control scheme of the drive utilizes the Digital Phase Locked Loop (DPLL). The DPLL is safely implemented all around the well known integrated circuit DPLL 4046. An experimental verification is carried out on one kw scalar controlled IM system drives for...