Cut-Through switching techniques, and Application Spec@ic Integrated Circuit (ASIC)-based wire-speed routing both attempt to improve network pe~ormance whenever possible. While switching advocates prefer the, “Route once, switch thereafter” approach, ASIC-based routing vendors believe the “Route wherever you wish” approach is the prevailing long-term solution. Both attempt to eliminate the cost...

This paper uses a CAD methodology proposed by the authors to design a low-power 2ndorder ΣΔM. This modulator has been fabricated in a 0.7μm CMOS technology to be used as the front-end of an energy metering mixed-signal ASIC and features 16.4bit at a digital output rate of 9.6kHz with a power consumption of 1.71mW. It yields a value of the figure which is the smallest reported to now, thus demon...

package technology and its design challenges E. D. Blackshear M. Cases E. Klink S. R. Engle R. S. Malfatt D. N. de Araujo S. Oggioni L. D. LaCroix J. A. Wakil G. G. Hougham N. H. Pham D. J. Russell This paper reviews sequential build-up (SBU) laminate substrate development from its beginning in 1988. It reports on developments in this technology for IBM applications since its adoption in 2000. ...

Bitcoin mining presents a significant economic incentive for efficient hashing and broadcast of data, both parameters stemming from the Proofs-of-Work used to advance the network. This incentive has led to the development of Bitcoin-specific application-specific integrated circuits (ASICs) and centralized mining pools, undermining the decentralized motivations behind Bitcoin’s design. In additi...

40 Manufacturers of application-specific integrated circuits (ASICs) face some unique yield-management challenges. At any given time, scores of different products and numerous different technologies may be moving through the manufacturing line – some ramping up, some already ramped, and some in a start-up phase. While any competitive semiconductor company must constantly refine and improve its ...

Physically-aware N-detect (PAN-detect) test improves defect coverage by exploiting defect locality. This paper presents physically-aware test selection (PATS) to efficiently generate PAN-detect tests for large industrial designs. Compared to traditional N-detect test, the quality resulting from PAN-detect is enhanced without any increase in test execution cost. Experiment results from an IBM in...

Authors James McDonald: Co-founder and president of Cactus Semiconductor, a fabless semiconductor firm that specializes in custom medical integrated circuits including ASICs used in implantable applications Steven Dean: Global medical market lead for Freescale David Niewolny: Medical segment manager with Freescale’s Microcontroller Solutions Group Donnie Garcia: Systems engineer with Freescale’...

A frontend Application Specific Integrated Circuit (ASIC) prototype developed for the read out of the CMS barrel muon drift tubes chambers has been produced in 100 samples. Several chips were used to read out one superlayer (224 drift tubes) of a full size prototype chamber. The properties of the chips and the performance of the chamber part equipped with the frontend prototype are presented.

In a VHDL-based design flow for application specific integrated circuits, VITAL provides a uniform methodology for developing ASIC libraries for signoff simulation. The VITAL Standard includes specialized routines for describing behavior and timing of ASIC cells and integrates backannotation via Standard Delay Format (SDF). One of the key issues of the VITAL initiative was to accelerate simulat...

With the increasing need of security, cryptographic processing becomes a crucial issue for network devices. Traditionally security functions are implemented with Application Specific Integrated Circuit (ASIC) or GeneralPurposed Processors (GPPs). Network processors (NPs) are emerging as a programmable alternative to the conventional solutions to deliver high performance and flexibility at moder...