Performance in IEEE 1588 synchronization depends on several related factors. Among them, the symmetry of packet delay is the most basic one. But most existing networks could not provide symmetry packet delay between master and slave clocks. From research we found that, FIFO waiting during packet transmitting is one of the main reasons that lead the asymmetry. This paper puts forward a packet de...

information asymmetry in stock market can increase the risk of investment which in turn increases the capital cost of firms. bhattacharya (1979) proposed a hypothesis that states dividend can act as a powerful signal in order to solve information asymmetry problem. we measured information asymmetry by lack of earnings transparency. therefore we examine the effect of earnings transparency on cap...

A bstrucrCIOB (Combined Input-Output Buffered) switches with a moderate speedup have been widely considered as the most feasiblesolution for large-capacity switches. In this paper, we adopt the hierarchical link sharing (HLS) algorithm in non-blocking CIOB switches to guarantee delay bound that is independent of the switch size. We also propose a feasible architecture to implement the HLS algor...

The increased dependence of clock cycle time on interconnect delay favors chip multiprocessors (CMP) as the basis for future microprocessor designs. The tight coupling of processing units in a CMP allows new forms of parallelism to be exploited. This paper studies multiple-path execution (MPE) on a CMP design to provide speedup on unmodified sequential code by exploring different paths of a con...

We study the effect of speedup on the dynamical behavior of a single cyclic bus in a bus system with many bus stops. We present a nonlinear-map model of a cyclic bus to take into account the speedup. When the cyclic bus is delayed, the bus speeds up to retrieve the delay. It is found that the cyclic bus exhibits chaotic motion with increasing speedup. The chaotic motion depends on both speedup ...

We develop an analytical delay model based on rst and second moments to incorporate inductance e ects into the delay estimate for interconnection lines. Delay estimates using our analytical model are within 15% of SPICE-computed delay across a wide range of interconnect parameter values. We also extend our delay model for estimation of source-sink delays in arbitrary interconnect trees. For the...

Hybrid switch architecture with electronic buffering/processing and optical switching fabric is receiving a lot of attention as potential candidate for the design of highperformance and scalable switches/routers. However, the reconfiguration overhead of optical fabrics brings new challenges to system and scheduling algorithm design. For example, speedup is compulsory to make the switch stable; ...

Previous work has shown that a system-on-a-chip lock cache (SoCLC) reduces on-chip memory traffic, provides a fair and fast lock hand-off, simplifies software, increases the real-time predictability of the system and improves performance. In this research work, we extend the SoCLC mechanism with a priority inheritance support implemented in hardware. Priority inheritance provides a higher level...

migraine is a neurologic disease, which often is associated with a unilateral headache. vestibular abnormalities are common in migraine. vestibular evoked myogenic potentials (vemps) assess otolith function in particular functional integrity of the saccule and the inferior vestibular nerve. we used vemp to evaluate if the migraine headache can affect vemp asymmetry parameters. a total of 25 pat...