This paper presents an automated procedure for the technology mapping of timed circuits to practical gate libraries. Timed circuits are a class of asynchronous circuits that incorporate explicit timing information in the speciication which is used throughout the design process to optimize the implementation. Our procedure begins with a timed speciication and a delay-annotated gate library descr...

The purpose of this monograph is to provide both an introduction to eld of asynchronous digital circuit design and an overview of the practical state of the art in 1997. In the early days of digital circuit design, little distinction was made between synchronous and asynchronous circuits. However, since the 1960's, the mainstream of the digital circuit design enterprise has been primarily conce...

This paper introduces a synthesis tool for template-based synthesis of asynchronous circuits. The tool, named Template Synthesizer (TSYN) and it is a part of a complete asynchronous design flow named Persia. This tool transforms a behavioral description of a circuit to a sized transistor net-list. The input behavioral description must fit into some previously known templates. These templates ar...

This paper shows how the application of a CMOS ternary logic is useful in the realisation of Delay Insensitive (01) asynchronous circuits. It is shown that fully DI asynchronous circuits are obtained with a ternary handshake protocol which employs the third logic level as idle state of the asynchronous interface. The advantages obtained are a dramatic reduction of the communication requirement ...

In this article, an alternative approach to detecting the computation completion of combinatorial blocks in asynchronous digital systems is presented. The proposed methodology is based on well-known phenomenon that occurs in digital systems fabricated in CMOS technology. Such logic circuits exhibit significantly higher current consumption during the signal transitions than in the idle state. Du...

Two solutions to the MUTEX-problem are compared w.r.t. their temporal eeciency. For this, a formerly developed eeciency testing for asynchronous systems is adapted to Petri nets with so-called read arcs. Furthermore, a com-positional semantics for fair behaviour (in the sense of the progress assumption) is presented. On the one hand, this semantics is related to eeciency testing; on the other h...

Based on a previously reported request driven technique for Globally-Asynchronous Locally-Synchronous (GALS) circuits this paper presents two significant enhancements. Firstly, the previously required local ring oscillators are avoided. Instead, an external clock with arbitrary phase for each GALS block is used. Details of the required wrapper circuitry, the proposed design flow and performance...

We consider the problem of synthesizing correct-by-construction globally asynchronous, locally synchronous (GALS) implementations from modular synchronous specifications. This involves the synthesis of asynchronous wrappers that drive the synchronous clocks of the modules and perform input reading in such a fashion as to preserve, in a certain sense, the global properties of the system. Our app...

The asynchronous systems are the models of the asynchronous circuits from the digital electrical engineering. An asynchronous system f is a multi-valued function that assigns to each admissible input u : R → {0, 1}m a set f(u) of possible states x ∈ f(u), x : R → {0, 1}n. A special case of asynchronous system consists in the existence of a Boolean function Υ : {0, 1}n × {0, 1}m → {0, 1}n such t...

In present paper, I propose a method for resolving the timing delays for output signals from an asynchronous sequential system. It will be used an example of an asynchronous sequential system that will set up an output signal when an input signal will be set up. The width of the output signal depends on the input signal width, and in this case it is very short. There are many synthesis methods,...