This paper presents a new method for designing asynchronous sequential circuits. The inspiration for this method is derived from the traditional synchronous design method. We introduce a new component which is used as a building block for sequential parts of asynchronous circuits. This new component is similar to the old Flip-Flop but it has the ability to handle signal edges asynchronously. Th...

Combinational logic synthesis is a very zmportant but compututionally expensive phase of VLSI system design. Parallel processing offers an attructive solution to reduce this design cycle time. In this paper; we describe ProperMIS, a portable parallel algorithm for logic synthesis based on the MIS multi-level logic synthesis system. As part of this work, we have developed novel parallel algorith...

This paper presents a novel FPGA architecture for implementing various styles of asynchronous logic. The main objective is to break the dependency between the FPGA architecture dedicated to asynchronous logic and the logic style. The innovative aspects of the architecture are described. Moreover the structure is well suited to be rebuilt and adapted to fit with further asynchronous logic evolut...

We proposed the method of two-level (AND-OR) implementation of minimized asynchronous logic functions. We formulated and proved the product term minimization constraint that ensures the logic correct behaviour. We pointed out the existing tool that yields the term minimization under the constraint formulated. We processed examples and generated asynchronous two-level logic by applying our appro...

The growing variability and complexity of advanced CMOS technologies makes the physical design of clocked logic in large Systems-on-Chip more and more challenging. Asynchronous logic has been studied for many years and become an attractive solution for a broad range of applications, from massively parallel multi-media systems to systems with ultra-low power & low-noise constraints, like cryptog...

As transistor switching speed improves, synchronizing a global clock increasingly degrades system performance. Therefore, self-timed asynchronous logic becomes potentially faster than synchronous logic. To do so, however, it must exploit the techniques used in fast synchronous designs, including: redundant logic, inverting logic, transistor size optimization, dynamic logic, and phase alignment....

Abstract: The use of asynchronous sequential circuits has brought many advantages to system development, given the following examples:  Signal interface protocols (for example SCSI)  Asynchronous circuits are ideal for building modular systems. This modular structure enables a global system time checkup. The asynchronous circuits developed for high performance systems, for speeds up to 75 MHz...

This paper presents a low-power FPGA based on mixed synchronous/asynchronous design. The proposed FPGA consists of several sections which consist of logic blocks, and each section can be used as either a synchronous circuit or an asynchronous circuit according to its workload. An asynchronous circuit is power-efficient for a low-workload section since it does not require the clock tree which al...