SR-IOV capable network devices offer the benefits of direct I/O throughput and reduced CPU utilization while greatly increasing the scalability and sharing capabilities of the device. SR-IOV allows the benefits of the paravirtualized driver’s throughput increase and additional CPU usage reductions in HVMs (Hardware Virtual Machines). SR-IOV uses direct I/O assignment of a network device to mult...

Semantics preserving compilation of low-level C programs is challenging because their semantics is implementation defined according to the C standard. This paper presents the proof of an enhanced and more concrete memory model for the CompCert C compiler which assigns a definite meaning to more C programs. In our new formally verified memory model, pointers are still abstract but are nonetheles...

Interpretation of Microcontroller Code: Intervals Meet Congruences Jörg Brauer, Andy King, Stefan Kowalewski Embedded Software Laboratory, RWTH Aachen University, Germany Portcullis Computer Security Limited, Pinner, UK Abstract Bitwise instructions, loops and indirect data access present challenges to the verification of microcontroller programs. In particular, since registers are often memory...

In existing multicomputers, software overhead dominates the message-passing latency cost. Our research on the SHRIMP project at Princeton indicates that appropriate network interface support can signi cantly reduce this software overhead. We have designed two network interfaces for the SHRIMP multicomputer. Both support virtual memory mapped communication allowing user processes to communicate ...

Memory-mapped networks such as Scalable Coherent Interconnect (SCI) [5] and Memory Channel [4] offer a new method for constructing network peripherals by remoting a host’s IO bus. This paper details our experiences from building such an endpoint, and examines how greater support may be provided.