This brief presents a new topology of a multibit quadrature band-pass sigma-delta modulator which employs a simple dynamic element matching (DEM) technique in order to reduce the effects of path mismatch, namely aliasing in the signal band of the mirror images of the signal and of the quantization noise. The DEM scheme results in a reduction of the aliasing of the quantization noise mirror imag...

This chapter presents the design of the track-and-hold and multiplying digital-to-analog converter functional blocks. They are realized by Switched Capacitors (SC) circuits. Typical SC circuit stage consists of sampling capacitors and Metal Oxide Semiconductor (MOS) switches which turn on and off at the clock rate to store the input signal (charge) on the sampling capacitors and subsequently tr...

In modular multilevel converters (MMCs), tem5 perature control of semiconductor devices in the submod6 ules (SMs) is a key factor for the safe and reliable opera7 tion. Under normal operation, significant temperature differ8 ences can exist between SMs due to, for example, aging of 9 semiconductor modules and module parameter mismatch. 10 This paper presents a method for achieving SM thermal ba...

optimal sitting and sizing of shunt capacitor banks at the distribution networks for the purpose of power quality improvement is drawn much attention of electric power utilities in the last decades. determining the optimal number, location and sizing of capacitor using bee colony optimization algorithm (bco) is being presented in this paper. the bco algorithm is a new population based meta-heur...

A 12-bit high-speed column-parallel two-step single-slope (SS) analog-to-digital converter (ADC) for CMOS image sensors is proposed. The proposed ADC employs a single ramp voltage and multiple reference voltages, and the conversion is divided into coarse phase and fine phase to improve the conversion rate. An error calibration scheme is proposed to correct errors caused by offsets among the ref...

Capacitor mismatch is the main source of nonlinearity for pipelined analog-to-digital (A/D) converters. Here a digital erroraveraging technique is presented to greatly reduce this effect. Compared to the conventional circuit, the new approach requires only one extra digital addition. This allows a very simple and compact implementation. On the other hand, the conversion speed is halved because ...

Micro power converters are required for power sensitive, battery-operated devices. Keeping this goal in mind IMT developed a 13-bit RSD cyclic converter. However, inaccuracies (capacitor mismatch, operation amplifier...) resulted in a relative precision behaviour. The implementation of a correction algorithm in a 2 μ m CMOS technology is presented. It requires 1 mm 2 and simulations show that p...

|The high-order modulator is an appropriate approach for high-bandwidth, high-resolution A/D conversion. However, non-ideal e ects such as the nite opamp gain and the capacitor mismatch have great impacts on its performance at a low oversampling ratio. To achieve greater performance under the inevitable non-ideal e ects, we explore several multiple-bit schemes, based on our CIQE high-order arch...

An algorithmic ADC that is insensitive to capacitor mismatch and finite opamp gain and offset is described. Using the differential sampling scheme with the correlated double sampling (CDS) technique together, the virtually errorfree and fast multiply-by-two operation is obtained for the proposed ADC. For an N-bit converter, a new output word is obtained every 4N clock periods, and this represen...