نتایج جستجو برای: chip
تعداد نتایج: 51516 فیلتر نتایج به سال:
newell's learning stages model is a learning model based on dynamic systems theory which is divided to three stages based on the relationship among learners' degree of freedom. the aim of this study was to investigate the effect of attention focus of instruction on learning a simple skill (throwing darts) and a complex skill (non-dominant foot chip shot). thestudyconsistedoftwoexperim...
increasing the number of cores integrated on a chip and the problems of system on chips caused to emerge networks on chips. nocs have features such as scalability and high performance. nocs architecture provides communication infrastructure and in this way, the blocks were produced that their communication with each other made noc. due to increasing number of cores, the placement of the cores i...
This paper presents design and characterization of NanoCu based ultra-fine pitch chip-to-package interconnects for microwave frequencies. Transitions are designed with this new interconnect and characterized upto 40 GHz in Packaging configurations such as Chip-on-Chip and Chip-onPackage.
The Multiscale Strip Construction, or in short MSC (Lerman et al., 2007), was initially proposed to identify enriched spots in ChIP-on-chip arrays. Here we extend this method to the setting of robust high-dimensional curve estimation. We establish its robustness as well as accurateness by bounding both the empirical influence function and the empirical bias of approximation at a sufficiently la...
در این پایان نامه مراحل طراحی یک vga (variable gain amplfier) یا تقویت کننده بهره متغیر توصیف گردیده است . برای طراحی این مدار از پروسس 0.5um در تکنولوژی cmos استفاده شده است . این vga بسیار خطی بوده و برای تغییرات بهره نیازی به خازن و مقاومت اضافی ندارد. این امر خود باعث کاهش سطح فعال (active area) تراشه (chip) و همچنین با عث کاهش توان مصرفی شده است . مدار دارای باندی پهن بوده و اندازه آن مستق...
in this paper, a new structure possessing the advantages of low-power consumption, less hardware and high-speed is proposed for fuzzy controller. the maximum output delay for general fuzzy logic controllers (flc) is about 86 ns corresponding to 11.63 mflips (fuzzy logic inference per second) while this amount of the delay in the designed fuzzy controller becomes 52ns that corresponds to 19.23 m...
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