 Conventional PLL design techniques used to implement CMOS GHz range clock recovery circuits typically suffer from significant power supply coupled noise in large integrated systems. This noise worsens the jitter of the PLL and degrades the system Bit-ErrorRate (BER). This paper describes an analog approach which applies fully differential current steering technique throughout the whole PLL sy...

An on-chip process, supply voltage, and temperature (PVT) compensation technique for low-voltage CMOS digital circuits was proposed. Because the degradation of circuit performance originates from the variation of the saturation current in transistors, we developed a compensation circuit consisting of a reference current that is independent of PVT variations. The circuit is operated so that the ...

A 2-digit higher radix analog-to-digital converter (ADC) circuit consisting of a combination of a pipelined ADC and a set of cascaded current comparator cell has been proposed. The ADC generates multi-valued logic outputs rather than the conventional binary output system. The design is implemented using 0.25μm CMOS process. The performance analysis of the design shows desirable performance para...

CMOS was developed as a digitally friendly process. Now, thanks to high levels of system integration and the emergence of SOC (system-on-chip) design, CMOS has also become the process of choice for mixed-signal applications. However, cutting-edge CMOS has limitations in these applications. Process restrictions, inaccurate simulation models, wide parametric variance, and noisy application enviro...

THIS special issue consists of papers which have been presented at the 23rd European Solid-State Circuits Conference, held September 16–18, 1997 in Southampton, U.K. Three hundred sixteen people attended this ESSCIRC conference, which has a strong focus on integrated circuit design, including sensor interfaces, various analog functions, communication circuits, mixed-signal systems, memories and...

An ideal CMOS analog switch would exhibit such characteristics as zero resistance when turned on, infinite resistance when turned off, zero power consumption, and zero switching time. Unfortunately, such a device is usually found as an example in a college textbook. The real world offers trade-offs and imperfections which prevent the realization of the ideal. The integrated circuit designer wor...

A 6-bit weighted-current-sink video digital-to-analog converter (DAC) with 10-90 percent rise/fall time of 4 ns, integrated with a double-metal 3pm CMOS technology, is described. Current-source matching, glitch reduction, and differential switch driving aspects are considered. A new circuit solution and a nonconventional layout technique yield a high conversion rate with a standard CMOS technol...

In mixed-signal designs, substrate coupling of digital circuit noise can severely compromise the behavior of sensitive analog circuits. Proper characterization of substrate noise is therefore indispensable. In this paper, we present an experimental setup for the characterization of directly coupled substrate noise in bulk-type CMOS. We have integrated configurable substrate noise generation and...