نتایج جستجو برای: cmos logic circuit
تعداد نتایج: 268369 فیلتر نتایج به سال:
In this paper, the design of a low power and high performance dynamic circuit using a new CMOS domino logic family called feedthrough logic is presented. The need for faster circuits with low power dissipation has made it common practice to use feedthrough logic. The proposed circuit for low power improves dynamic power consumption as compared to the existing feedthrough logic and improves its ...
The paper presents a new quasi adiabatic logic family that uses two complementary split-level sinusoidal power supply clock for digital low power applications such as sensors. The proposed two-phase adiabatic static CMOS logic circuit (2PASCL) is using the principle of energy recovery and adiabatic switching. It has switching activity that is lower than dynamic logic and can be directly derived...
This paper addresses power consumption in CMOS logic gates through an study considering the design and technology points-of-view. Through SPICE simulations, the relationship between charge/discharge and short-circuit components of dynamic power consumption are investigated both considering different logic gates and its evolution through technology scaling. Experimental results show that dynamic...
Static CMOS logic style is often the choice of designers for synthesizing low power circuits. This style is robust in terms of noise integrity however, it offers less speed. Domino logic style, as an alternative is often found in critical paths of various large scale high performance circuits. Yet, due to high switching activity they are not suitable for synthesis of low power circuits. To achi...
Domino CMOS logic circuit family finds a wide variety of applications in microprocessors, digital signal processors, and dynamic memory due to their high speed and low device count. These dynamic circuits are often favored in high performance designs because of the speed advantage offered over static CMOS logic circuits. In this paper, AND gates with different body
In this paper, a new structure possessing the advantages of low-power consumption, less hardware and high-speed is proposed for fuzzy controller. The maximum output delay for general fuzzy logic controllers (FLC) is about 86 ns corresponding to 11.63 MFLIPS (fuzzy logic inference per second) while this amount of the delay in the designed fuzzy controller becomes 52ns that corresponds to 19.23 M...
Dynamic domino logic circuits are widely used in modern digital VLSI circuits. These dynamic circuits are often favored in high performance designs because of the speed advantage offered over static CMOS logic circuits. The main drawbacks of dynamic logic are a lack of design automation, a decreased tolerance to noise and increased power Consumption. Dynamic CMOS circuits, featuring a high spee...
We have proposed a new concept of 3D architecture using four-terminal electrical switches (FES), which can replace CMOS logic without self-organized bottom-up process. Ultra high speed FES can be realized by nanoscale electrical mechanical system based on carbon nanotube. Nonvolatile FES can also be realized by modifying twoterminal nonvolatile memory devices, such as solid electrolyte memory u...
چکیده ندارد.
The purpose of this paper is to design a 64×64 bit low power, low delay and high speed Arithmetic Logic Unit (ALU). Arithmetic Logic Unit performs arithmetic operation like addition, multiplication. Adders play important role in ALU. For designing adder, the combination of carry lookahead adder and carry select adder, also add-one circuit have been used to achieve high speed and low area. In mu...
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