A digital delay-locked-loop (DLL) suitable for generation of multiphase clocks in applications such as timeinterleaved and pipelined ADCs locks in a very wide (40X) frequency range. The DLL provides 12 uniformly delayed phases that are free of false harmonic locking. The digital control loop has two stages: a fast-locking coarse acquisition is achieved in four cycles using binary search; a fine...

Dual threshold voltages domino design methodology utilizes low threshold voltages for all transistors that can switch during the evaluate mode and utilizes high threshold voltages for all transistors that can switch during the pre charge modes. We employed standby switch can strongly turn off all of the high threshold voltage transistors which enhances the effectiveness of a dual threshold volt...

In this paper, a thorough analysis of the jitter behavior of a Delay Locked Loop (DLL) based clock multiplying architecture is presented. The noise sources that are included in the analysis are the noise of the delay elements, the reference jitter and the noise of the Phase Frequency Detector and Charge Pump combination. It is shown that the effect of all noise sources on the output timing jitt...

Received Mar 17, 2017 Revised Sep 8, 2017 Accepted Sep 20, 2017 Delay locked loop is a critical building block of high speed synchronous circuits. An improved architecture of amixed signaldelay locked loop (DLL) is presented here. In this DLL, delay cell based on single ended differential pair configuration is used for voltage controlled delay line (VCDL) implementation. This delay cell provide...

In this paper a new non-coherent architecture for GNSS tracking loops is proposed and analyzed. A non-coherent phase discriminator, able to extend the integration time beyond the bit duration is derived from the Maximum Likelihood principle and integrated into a Costas loop. The discriminator is non-coherent in the sense that the bit information is removed by using a non-linear operation. By jo...

The phase-locked loop (PLL) propagation time is important unavoidable factor for high-speed coherent detection systems using broad-linewidth laser diodes. This paper report the linewidths requirements and the power penalties taking into account the loop propagation delay. The coherent optical receivers with PLL, based on Costas loop or decision driven loop (DDL) are taken into consideration. Th...

A Delay (D) flip-flop is an edge triggering device. A high speed, low power consumption, positive edge triggered conventional Delay (D) flip-flop can be designed for increasing the speed of counter in Phase locked loop, using 32nm CMOS technology. The conventional D flip-flop has higher operating frequencies but it features static power dissipation. The designed counter can be used in the divid...

Location estimation in Wireless networks has become an important feature for improvement in public safety service. Its potential applications include location sensitive billing, asset tracking, fraud protection, mobile yellow pages, fleet management, etc. Several location techniques using terrestrial wireless network elements and radio signals have been proposed over the years, but multipath pr...