In this paper, a novel class of Sigma-Delta modulators is presented. The usual scalar 1-bit quantizer in a Sigma-Delta modulator is replaced by a 1-bit vector quantizer with a Ndimensional input statevector from the linear feed-back fdter. Generally, the vector quantizer changes the nonlinear dynamics of the modulator, and a proper choice of vector quantizer can improve both system stabilitg an...

In this chapter we present an unified approach for study the stability and validation of potential limit cycles of one bit high order Sigma-Delta modulators. The approach is general because it uses the general form of a Sigma-Delta modulator. It is based on a parallel decomposition of the modulator and a direct nonlinear systems analysis. In this representation, the general N-th order modulator...

A major drawback of delta-sigma modulation is the high oversampling ratios required, especially for single-bit quantization. Accordingly, much of the research in the area has focused on lowering the sampling rate through various parallelization approaches. However, this research has been overwhelmingly concentrated on continuous and discrete-time analog modulator implementations for A/D convert...

Modulator is one of the most significant building-blocks in integrated discrete time component used in Sigma-Delta (ΣΔ) analog to digital converter. In this paper a novel structure of a switched-capacitor discrete time first order modulator Sigma-Delta is implemented at a supply voltage of 3 V. In addition, our design uses a Miller operational transconductance amplifier topology for low power c...

The DC content in single-bit domain is both undesirable and hard to remove. In this paper we propose a single-bit multiplierless DC-blocker structure. The input is assumed to be sigma-delta modulated bitstream. This DC-blocker is designed using a delta modulator topology with a sigma-delta modulator (SDM) embedded in its feedback path. Its performance is investigated in terms of the overall sig...

This paper presents the design and simulations results of a switched-capacitor discrete time Second order Sigma-Delta modulator used for a resolution of 14 bits Sigma-Delta analog to digital converter. The use of operational amplifier is necessary for low power consumption, it is designed to provide large bandwidth and moderate DC gain. With 0.35μm CMOS technology, the ΣΔ modulator achieves 86 ...

A low-voltage low-power discrete time sigma delta modulator for biomedical signal acquisition designed and implemented in 0.18-μm CMOS process is presented in this paper. This sigma delta modulator is designed using cascaded 3rd-order feedback form of integrator with the over sampling ratio (OSR) of 32. The experimental prototype chip achieves 55dB and 60dB dynamic range for 200Hz and 500Hz sig...

In this paper, a new approach for design of a fully differential second order current mode continuous-time sigma-delta modulator is presented. For circuit implementation, square root domain (SRD) translinear loop based on floating-gate MOS transistors that operate in saturation region is employed. The modulator features, low supply voltage, low power consumption (8mW) and high dynamic range (55...

A behavioral model of a second order switchedcapacitor Sigma-Delta modulator is presented. The purpose of this work is the presentation of a behavioral model of a second order switched capacitor ΣΔ modulator considering (Error due to Clock Jitter, Thermal noise Amplifier Noise, Amplifier Slew-Rate, Non linearity of amplifiers, Gain error, Charge Injection, Clock Feedthrough, and Nonlinear on-re...

This paper presents a circuit including a high-pass Σ∆ modulator implemented in CMOS process and a timeinterleaved high-pass Σ∆ analog to digital converter.