Abslruer-An all-digital architecture is presented for implementing the front-end signal processing functions in a quadrature modulator and demodulator for high bit-rate digital radio applications. A pair of CMOS chips has been designed and submitted for fabrication in a 1.25 pm process and is expected to accommodate symbol rates up to 35 MBd. The modulator chip accepts a pair of 8 b in-phase an...

Single-chip, low-power, programmable digital signal processing systems are capable of hosting complete speech processing applications, while consuming a few milliwatts of average power. We present a power management architecture that decreases the average power consumption of these systems to 3–10 microwatts, in applications where speech signals are present with a sufficiently low duty cycle. I...

This article introduces a power-efficient, miniature electronic nose (e-nose) system. The e-nose system primarily comprises two self-developed chips, a multiple-walled carbon nanotube (MWNT)-polymer based microsensor array, and a low-power signal-processing chip. The microsensor array was fabricated on a silicon wafer by using standard photolithography technology. The microsensor array comprise...

Low power and high throughput digital systems are required in the number of applications such as Computer Graphics, Virtual Reality, System Control, Image Processing, and Digital Signal Processing etc. The various approaches suggested by researchers for power efficient high throughput architectures include pipelining, parallelism, retiming, folding-unfolding, using multiprocessor environment et...

Seismic acquisition and monitoring system can collect, store, analyze and dispose the rock burst seismic waves or the vibration of other objects. This paper utilizes single chip computer technology, virtual instrument technology, sensor technology, database management technology, wavelet analysis technology, combining the real condition of the mine microseismic signal to establish a set of mine...

It is our opinion that the system-on-chip, all-in-one approach to parallel digital signal processing combining the homogeneous processor array with large amounts of data memory, will be the core of future embedded digital signal processing applications. In this paper we present two radical approaches to efficient system-on-chip (SoC) design with homogeneous processor arrays for real-time applic...

A board is described that contains the ANN A neural-network chip, and a DSP32C digital signal processor. The ANNA (Analog Neural Network Arithmetic unit) chip performs mixed analog/digital processing. The combination of ANNA with the DSP allows high-speed, end-to-end execution of numerous signal-processing applications, including the preprocessing, the neural-net calculations, and the postproce...