A new fault tolerant multipipeline array architecture and its diagnosis/reconfiguration algorithm will be presented. This multipipeline array design methodology is characterized by constant, fault distribution independent interstage path lengths. Other features include a low hardware overhead and a high survival rate when it is compared to existing approaches.

Achieving fault-tolerance through incorporation of redundancy and reconfiguration is quite common. The distribution of faults can have several impacts on the effectiveness of any reconfiguration scheme; in fact, patterns of faults occurring at strategic locations may render an entire VLSI system unusable regardless of its component redundancy and its reconfiguration capabilities. Such fault pat...

Field Programmable Gate Array (FPGA) market is growing rapidly with various applications in different industries. There is a new concept evolving in FPGA industry called Dynamic Partial Reconfiguration (DPR) with has a greater exposure in different applications. Partial reconfiguration is nothing but reconfiguring the selected areas of an FPGA after its initial configuration at runtime. In this...

In a vessel, the Shipboard Power System (SPS) is responsible for supplying energy to various services, such as navigation and communication. A research topic is the reconfiguration of the electrical scheme in case of either failure or damage. Indeed, after a fault, the software control system must ensure the ship’s survival. In a couple of earlier studies, we: (i) analyzed the relation between ...

F ield programmable gate array (FPGA) components are widely used nowdays to implement various algorithms, such as digital filtering, in real time. The emergence of dynamically reconfigurable FPGAs made it possible to reduce the number of necessary resources to carry out an image-processing task (tasks chain). In this article, an image-processing application, image rotation, that exploits the FP...

In order to address the issue of power loss resulting from partial shadow and enhance efficiency photovoltaic generation, array reconfiguration technology is being increasingly utilized in generation systems. This paper proposes a method based on improved hybrid particle swarm optimization (HPSO) for TCT (total-cross-tied) structure. The motivation behind this get best scheme simple efficient m...

This report presents a configuration memory architecture that offers fast FPGA reconfiguration. The underlying principle behind the design is the use of fine-grained partial reconfiguration that allows significant configuration re-use while switching from one circuit to another. The proposed configuration memory works by reading on-chip configuration data into a buffer, modifying them based on ...

In this work, the method of iterative Fourier transform phase reconstruction, conventionally used in holography and optical image reconstruction, is applied to phase only synthesis of antenna patterns. The method is applied to two types of pattern synthesis problems: "main lobe beam shaping" and "side-lobe-level reduction". The proposed method is most useful in the efficient employment of attai...

Thermoelectric generation (TEG) has increasingly drawn attention for being environmentally friendly. A few researches have focused on improving TEG efficiency at system level on vehicle radiators. The most recent reconfiguration algorithm shows improvement on performance but suffers from major drawback on computational time and energy overhead, and non-scalability in terms of array size and pro...

Optically Reconfigurable Gate Arrays (ORGAs), by exploiting the large storage capacity of holographic memory, offer the possibility of providing a virtual gate count that is much larger than those of currently available VLSI circuits. In such cases, because circuits implemented on a gate array often must be changed with virtual circuits stored in a holographic memory, rapid reconfiguration is n...