A fast algorithm for the fault simulation using data level parallelism is implemented on the Connection Machine. The algorithm employed is the PPSFP (Paralle l Pattern Single Fault Propagation) type. The input of the algorithm is the PI (Primary Input) test patterns obtained from a cellular automata pseudo-random pattern generator. The output of this system is a fault simulation table that desc...

A new technique is proposed to handle fault simulation at the architectural level. The technique bypasses the need for complete gate-level structure and ee-ciently uses the architectural information. Symbolic data representing groups of stuck-at faults, known as fault eeects, are propagated across the circuit with intelligent propagation prediction. Fault eeects may combine and form new groups ...

this paper presents the application of radial basis neural networks to the development of a novel method for the condition monitoring and fault diagnosis of synchronous generators. in the proposed scheme, flux linkage analysis is used to reach a decision. probabilistic neural network (pnn) and discrete wavelet transform (dwt) are used in design of fault diagnosis system. pnn as main part of thi...

We present stuck-at and bridging fault simulation results for previously proposed Built-In Self-Test (BIST) approaches for the programmable interconnect resources in Field Programmable Gate Arrays (FPGAs). In addition, new BIST approaches are proposed and analyzed via fault simulation. The fault simulation results are used to compare and evaluate the fault detection capabilities and effectivene...

This paper describes an environment to accelerate fault simulation by hardware emulation on FPGA. Fault simulation is an important subtask in test pattern generation and it is frequently used throughout the test generation process. The problems associated with fault simulation of digital circuits are explained. The proposed approach allows simulation speed-up of 40 to 500 times as compared to t...

The fault coverage of a random test can be estimated by fault simulation. If the simulation is performed by another random sequence than those used under test or a fault sample is used, a random difference between the simulation result and the fault coverage has to be considered. The simulation result must be larger than the fault coverage that has to be guaranteed. The difference is called gua...

In the case of digital circuits, the possible defects in a circuit may be modelled by faults such as the singlestuck fault model and bridging faults. Thus a very large numbe of possible defects may be reduced to a relatively small number of faults. In digital fault simulation, a number of copies of the circuit are made, each of which contains exactly one fault, together with the fault-free circ...

ESIM is a simulation tool that integrates logic fault and design error simulation for logic circuits. It targets several design error and fault models, and uses a novel mix of simulation algorithms based on parallel-pattern evaluation, multiple error activation, single fault propagation, and critical path tracing. Several experiments are discussed to demonstrate the power of ESIM.

This paper presents a new observer design methodology for a time varying actuator fault estimation. A new linear matrix inequality (LMI) design algorithm is developed to tackle the limitations (e.g. equality constraint and robustness problems) of the well known so called fast adaptive fault estimation observer (FAFE). The FAFE is capable of estimating a wide range of time-varying actuator fault...

In this paper, a new very fast fault simulation method to handle the X-fault model is proposed. The method is based on a two-phase procedure. In the first phase, a parallel exact critical path fault tracing is used to determine all the detected stuck-at faults in the circuit, and in the second phase a postprocess is launched which will determine the detectability of X-faults. Keywords-digital c...