Fault tolerance plays a major role in quantum computer design. As the quantum environment is not stable enough when the information is read from it, better designs with error correcting capability have to be designed to overcome the information loss due to decoherence in quantum circuits. This paper presents one such fault tolerant design using a new reversible gate.

The use of fault-tolerance structures in multiple processors systems due to the fact that it is almost impossible to manufacture integrated circuits without any defect in nanometer technologies [1]. As a result, the use of fault tolerant methods is crucial to allow that circuits with some amount of defects still reach the market, increasing yield and the lifetime of a chip. A classical example ...

We introduce a new model of fault tolerance for Boolean circuits. We consider synchronized circuits and we allow an adversary to choose a small constant fraction of the gates at each level of the circuit to be faulty. We require that even in the presence of such faults the circuit compute a \loose version" of the given function. We show that every symmetric function has a small (size O(n), dept...

For ordinary circuits with a xed upper bound on the fanin of its gates it has been shown that logarithmic redundancy is necessary and suucient to overcome random hardware faults (noise). Here, we consider the same question for unbounded fanin circuits which in the fault-free case can compute Boolean functions in sublogarithmic depth. Now the details of the fault model become more important. One...

Quantum computation is a recently-introduced and novel computing technique which is based on quantum mechanics rather than classical physics. Its starting point is the notion of a quantum bit or “qubit”. Because of the superposition property of quantum states, n qubits can store 2 n numbers simultaneously, implying a type of massive parallelism. Furthermore, quantum states allow powerful forms ...

This paper presents a design methodology for fault tolerant sequential systems implemented on System on Chip (SoC). In the paper, as an example, a complex fault tolerant finite state machine has been mapped on the FPGA contained in the SoC. The fault identification has been obtained by using a checker permitting the identification of class of faults. When a fault is detected, an interrupt for t...