Testability analysis of basic and complex logic gates employing complementary pass transistor logic (CPL) under various single stuck faults is investigated. Results show that all stuck-on faults, bridging faults and more than 90% stuck-at faults in the basic CPL gates are only detectable by current monitoring generally known as IDDQ testing. It is also shown that all stuck-open faults in the ba...

Fault-tolerant quantum circuit design can be done by using a set of transversal gates. However, as there is no error correction code with universal gates, several approaches have been proposed which, in combination make fault-tolerant computation possible. Magic state distillation, gauge fixing, switching, concatenation and pieceable fault tolerance are well-known examples such approaches. the ...

In this paper, logical masking capability of commonly used logic gates such as NOT, AND/NAND, OR/NOR, and XOR/XNOR, when subject to single/multiple input faults, are analyzed from a mathematical perspective. A new metric, called Gate Error Metric (GEM) is proposed to study the extent of output error in these gates when subject to potential input fault occurrences, where less value of GEM implie...

One of the important tasks of the Reliability Estimation is Analysis of the Fault Tree. A problem of Fault Trees analysis is considered one of the most complex ones, since structure of such trees is characterized by a considerable number of interconnections. Usually analytical methods are used and most applicable method is Minimal Cut Sets building and calculation. Classical Fault Tree Analysis...

In many of cryptographic schemes, the most time consuming basic arithmetic operation is the finite field multiplication and its hardware implementation may require millions of logic gates. It is a complex and costly task to develop such large finite field multipliers which will always yield error free outputs. In this effect, this paper considers fault tolerant multiplication in finite fields. ...

Making a reversible circuit fault-tolerant is much more difficult than classical circuit and there have been only a few works in the area of parity-preserving reversible logic design. Moreover, all of these designs are ad hoc, based on some pre-defined parity preserving reversible gates as building blocks. In this paper, we for the first time propose a novel and systematic approach towards pari...

Abstract— In this paper, the researchers propose the design of reversible circuits using reversible gates. Reversible logic is implemented in reversible circuits. Reversible logic is mostly preferred due to less heat dissipation. Conservative logic gates can be designed in any sequential circuits and can be tested using two test vectors. The significance of proposed work lies in the design of r...

We propose a new class of unconventional geometric gates involving nonzero dynamic phases, and elucidate that geometric quantum computation can be implemented by using these gates. Comparing with the conventional geometric gate operation, in which the dynamic phase shift must be removed or avoided, the gates proposed here may be operated more simply. We illustrate in detail that unconventional ...