In this paper, a preprocessing circuit for ISFETs (Ion-sensitive field-effect transistors) to measure hydrogen-ion concentration in electrolyte is presented. A modified flip-flop is the main part of the circuit. The modification consists in replacing the standard transistors by ISFETs and periodically switching the supply voltage on and off. Concentration of hydrogen ions to be measured discont...

Providing resistance against side channel attacks especially differential power analysis (DPA) attacks, which aim at disclosing the secret key of cryptographic algorithm is one of the biggest challenges of designers of cryptographic devices. In this paper design of novel data flip-flop compatible with three-phase dual-rail logic (TDPL), called Charge recycling TDPL flip-flop is investigated. Th...

Activating a flip-flop circuit by a current fast-rising slope impulse, the circuit occupies one of the two stable states, the stable state ‘one‘ or ‘zero‘. In case of a perfect flip-flop symmetry over a large number of cycles, a noise causes the ratio of ‘ones‘ and ‘ zeros‘ is equal to one – 50% position of a flip-flop. However, any imbalance in the system changes the probability of taking a ‘o...

Clustered voltage scaling scheme is an effective method of power consumption reduction without performance degradation. One of the main issues in this scheme is performance and power penalties due to insertion of level converting flip-flops at the interface from low-supply to high supply clusters to simultaneously perform latching and level converting functions. A new level converting flip-flop...

For the first time an all optical flip-flop is demonstrated based on two coupled Mach-Zehnder interferometers which contain semiconductor optical amplifiers in their arms. The flip-flop operation is discussed and it is demonstrated using commercially available fiber pigtailed devices. Being based on Mach-Zehnder interferometers, the flip-flop has potential for very high speed operation. E-mail:...

The paper proposed a new design for implementing a Single Edge Triggered Flip-Flop. In this work, comparative analysis of six existing flip-flop designs along with the proposed design is made. In the proposed design the number of clocked transistors is reduced to decrease the power consumption and it also employs the conditional feedback to reduce the short-circuit currents. All simulations are...

Abstract: In this paper we present a simple ultra low-voltage and high speed D flip-flop. The delay of the static differential flip-flop presented is less than 12% compared to conventional differential CMOS flip-flops. The presented circuits have been simulated using Hspice and are valid for 90nm TSMC CMOS process. The proposed high-speed and ultra low-voltage flip-flop can be used for any digi...