In this paper we present a design for a floating point unit partially compliant with the IEEE 754 floating point standard. The unit fully implements comparisons and partially implements floating-point addition and multiplication. It is fully parametrized and may be used with floating point numbers whose composite fields have widths of any desired length.

OVERVIEW FPGAs are increasingly used as parallel processing engines for demanding digital signal processing applications. Benchmark results show that on highly parallelizable workloads, FPGAs can achieve higher performance and superior cost/performance compared to digital signal processors (DSPs) and general-purpose CPUs. However, to date, FPGAs have been used almost exclusively for fixed-point...

a multiple-unit oral floating system was prepared using the emulsification-solvent diffusion method to prolong the gastric emptying time of theophylline. for this purpose, theophylline, ethyl cellulose and dibutyl phthalate were dissolved in an ethanol/dichloromethane mixture, added to 0.1 m hcl containing nacl (20%) or saturated theophylline and/or different concentrations of polysorbate 80 an...

This paper presents complete processor hardware with three arithmetic units. The first arithmetic unit can perform 32-bit integer arithmetic operations. The second unit can perform arithmetic operations such as addition, subtraction, multiplication, division, and square root on 32-bit floating point numbers. The third unit can perform arithmetic operations such as addition, subtraction, multipl...

[Purpose] This study investigated the association between floating toe and toe grip strength. [Subjects and Methods] A total of 635 Japanese children aged 9-11 years participated in this study. Floating toe was evaluated using footprint images, while toe grip strength was measured using a toe grip dynamometer. All 1,270 feet were classified into a floating toe group and a normal toe group accor...

Due to technological advances, it has become possible to implement floating-point cores on FPGAs in an effort to provide hardware acceleration for the myriad applications that require high performance floating-point arithmetic. However, in order to achieve a high clock rate, these floating-point cores must be deeply pipelined. Due to this deep pipelining and the complexity of floating-point ari...

In this paper, we propose an architecture/methodology for making FPGAs suitable for integer as well as variable precision floating point multiplication. The proposed work will of great importance in applications which requires variable precision floating point multiplication such as multi-media processing applications. In the proposed architecture/methodology, we propose the replacement of exis...

Cell fate decisions in early embryonic cells are controlled by interactions among developmental regulatory genes. Zebrafish floating head mutants lack a notochord; instead, muscle forms under the neural tube. As shown previously, axial mesoderm in floating head mutant gastrulae fails to maintain expression of notochord genes and instead expresses muscle genes. Zebrafish spadetail mutant gastrul...

A new generation method to implement CMOS floating resistors is presented. The generation method depends on the linearization of the differential current of two matched NMOS transistors in two alternative configurations. The CMOS floating resistors implemented are based on using MOS transistors operating in the saturation region with their sources connected to their substrates. New CMOS floatin...