A class-AB four-quadrant current multiplier constituted by a class-AB current amplifier and a current splitter which can handle input signals in excess of ten times the bias current is presented. The proposed circuit operation is based on the exponential characteristic of BJTs or subthreshold MOSFETs. The multiplier is designed using the latter devices and achieves very low power consumption. S...

A high-speed analog VLSI image acquisition and low-level image processing system are presented. The architecture of the chip is based on a dynamically reconfigurable SIMD processor array. The chip features a massively parallel architecture enabling the computation of programmable mask-based image processing in each pixel. Extraction of spatial gradients and convolutions such as Sobel operators ...

Power consumption is the major issue in VLSI design. In this paper an efficient low power first order sigma delta modulator is designed for oversampled ADC using floating gate folded cascode operational amplifier, in 0.35 μm Technology. Floating gate MOSFET have low power Dissipation hence it is an attractive solution in design of data converters, low voltage op -amp with rail-to-rail input and...

In this paper we describe a CMOS differential active load and show how it can be used to create various useful structures. Tunable current gain stages and current squaring circuits are discussed. Their connection to a differential pairbased transconductor results in broad-range tunable transcon­ ductor structures suitable for adaptive continuous-time filtering applications and a four-quadrant v...

information into the cell body, and transmit the output electrical signals through the axon. The paper describes a VLSI design methodology for the implementation of analog artificial neural networks. Analog VLSI circuit techniques offers area-efficient implementation of the functions required in a neural network such as multiplication, summation and Sigmoid transfer function. However, the analo...

A CMOS low-power four-quadrant multiplier for Ultra-Wide Band (UWB) systems using FM-UWB and Impulse Radio (IR) is presented. A set of transconductors, rather than the traditional Gilbert cell, is employed. The configuration is simple and area saving. The simulated result shows: An average gain of 22.5 dBV−1 and 20.8 dBV−1 in the bandwidth of 700 MHz at 1.2 GHz and 4 GHz center frequencies, res...

A low-voltage analog multiplier operating at 1.2V is presented. The multiplier core consists of four MOS transistors operating in the saturation region. The circuit exploits the quadratic relation between current and voltage of the MOS transistor in saturation. The circuit was designed using standard 0.6μm CMOS technology. Simulation results indicate an IP3 of 4.9dBm and a spur free dynamic ran...

A novel 4-quadrant analog multiplier using Floating Gate MOS (FGMOS) transistors operating in saturation region are implemented. Floating gate MOSFETs are being utilized in a number of new and existing analog applications. These devices are not only useful for designing memory elements but also we can implement circuit elements. The main advantage in FGMOS is that the drain current is proportio...