A 6.0-13.5 GHz Alias-Locked Loop (ALL) frequency synthesizer is designed and simulated in 130 nm CMOS. Using an aliasing divider, the ALL architecture makes it possible to create high-speed frequency synthesis circuits without relying on a traditional divider clocked at fV CO in the feedback path. In this implementation, a new architecture of high frequency ring oscillator is proposed with a fe...

The demand for lower cost, lower power, and multiband RF circuits increased in conjunction with need of higher level of integration. In this project a low-power singlephase clock multiband flexible divider for Bluetooth, Zigbee, and Network standard’s 802.15.4 and 802.11 a/b/g Wireless LAN frequency synthesizers is proposed based on pulse-swallow topology and is implemented. The frequency synth...

This letter presents miniaturized Gysel power dividers using lumped-element components. The characteristic impedances of all the equivalent transmission lines in these dividers are fixed to the same values based on even and odd mode analysis, thus simplifying the design procedure and miniaturizing the Gysel power dividers. The ideal divider designed at a frequency of 590MHz exhibits power split...

This paper discussed the circuit level design and simulation of fractional-N frequency divider, a circuit block used mainly in frequency synthesizer. The design was done in schematic level. A low power 0.5 micron CMOS technology called CMOSIS5 used for modeling the circuit devices. The frequency divider was design for 900 MHz GSM standard mobile communication application. For the simulation, ci...

An ultra-wideband unequal-split Wilkinson power divider with a 2:1 split ratio is presented. To achieve the ultra-wideband characteristics, the conventional quarter-wave arms of the divider are replaced by tapered lines. Moreover, two extra tapered transformers are incorporated at the output ports for matching purposes as the designed divider is of an unequal-split type. To obtain good isolatio...

A simple odd number frequency divider with 50% duty cycle is presented. The odd number frequency divider consists of a general odd number counter and the proposed duty cycle trimming circuit. The duty cycle trimming circuit can output 50% duty cycle with only additional six transistors. A prototype divide-by-5 circuit with 50% duty cycle was implemented for a 500-Mb/s ∼ 5.6-Gb/s 1:10 CDR/DEMUX ...