This paper presents pre-layout simulations of a proposed 8T full adder design using a proposed 3T XNOR gate cell. The proposed design remarkably reduces power consumption hence power-delay product (PDP) over various input voltages and frequencies. It also improves temperature sustainability as compared to the existing 8T full adder. This proves to be a viable option for low power and energy eff...

Since in designing the full adder circuits, full adders have been generally taken into account, so as in this paper it has been attempted to represent a full adder cell with a significant efficiency of power, speed and leakage current levels. For this objective, a comparison between five full adder circuits has been provided. Applying floating gate technology and refresh circuits in the full ad...

This paper presents comparative study of high-speed, low-power and low voltage full adder circuits. Our approach is based on XOR-XNOR design full adder circuits in a single unit. A low power and high performance 9T full adder cell using a design style called “XOR (3T)” is discussed. The designed circuit commands a high degree of regularity and symmetric higher density than the conventional CMOS...

In this paper, we propose a novel multiplexer-based full adder design, denoted as MUXFA, by using regular modules for arithmetic applications. The MUXFA full adder is composed of three identical modules, in which each module separately operates for XOR-XNOR function, sum function, and carry function. The structure of the multiplexer-based full adder can be easily constructed by merely a single ...

This paper presents a novel low-power and high-speed 1-bit full-adder, which is designed based on pass transistor and TG logics. The main advantage of this design is low propagation delay and lowpower consumption, which leads to achieving lower PDP than others. Intensive HSPICE simulation shows that the new full-adder consumes around 28.5% less power than 14T adder; moreover its PDPis 30% less ...

Adiabatic logic is used to minimize the energy loss during operation of the circuit. Using two-phase adiabatic static CMOS logic (2PASCL) the power consumption can be reduced. This paper compares the power consumption of Static Energy Recovery Full Adder(SERF) and the proposed full adder using two phase adiabatic static CMOS logic(2PASCL). The average power consumption of proposed full adder is...

Full Adder is the basic building block for various arithmetic circuits such as compressors, multipliers, comparators and so on. 1-bit Full Adder cell is the important and basic block of an arithmetic unit of a system. Hence in order to improve the performance of the digital computer system one must improve the basic 1-bit full adder cell. In this, Full Adder is designed by using Hybrid-CMOS log...

This paper describes the speed of the design is limited by size of the transistors, parasitic capacitance and delay in the critical path. Power consumption and speed are two important but conflicting design aspects; hence a better metric to evaluate circuit performance is power delay product (PDP).The driving capability of a full adder is very important, because, full adders are mostly used in ...