In this paper, we discuss some aspects of using GALS in an FPGA. An introduction is given to the problems that occur when asynchronous circuit is used in a synchronous design environment. A short overview of existing communication ports close to our communication port is given. A limited part of the IEEE 802.11a transmitter has been implemented using GALS in an FPGA.

Complex SoC imply the seamless integration of numerous IPs performing different functions and operating at different clock frequencies. The integration of several heterogeneous components into a single system gives rise to new challenges. Major issue includes controlling the clock frequencies of the different modules. As chips become faster and larger, designers face significant challenges incl...

This paper gives a summary of the GALS methodology developed at the Swiss Federal Institute of Technology (ETH), Zurich. This methodology has been used to design and fabricate a test-bed for an asynchronous multi-point interconnect system, consisting of 25 GALS modules. In addition to the description of the design flow, based on the experience of this recent design, remaining problems from a de...

Globally Asynchronous Locally Synchronous (GALS) systems are popular both in software and hardware for specifying and producing embedded systems as well as electronic circuits. In this paper, we propose a method for obtaining automatically a GALS system from a centralised synchronous circuit. We focus on an algorithm that takes as input a program whose control structure is a synchronous sequent...

Significant efforts have been put into optimization of GALS systems by considering locally synchronous modules as individual and independent islands of circuits. While existing approaches do improve some of the system characteristics, due to their limited scope, their achieved improvement is often limited too. This paper proposes an optimization approach in which a GALS system is optimized as a...

In this paper we present a novel design approach that combines the advantages of on-chip switched networks (OCSNs) and the globally asynchronous, locally synchronous (GALS) design methodology using the mechanism of asynchronous FIFO buffers. Our proposed two GALS OCSN models were synthesized with 0.25μm Chip Express structured ASIC library. Comparative simulations were performed for these two p...

We present a design methodology that has been employed on a GALS test chip with three million transistors using a 0 25μm CMOS technology. The chip contains 25 GALS modules interconnected using four different bus architectures, various additional test stuctures, and occupies a total area of 25mm2. Hierarchical composition and timing verification, in conjunction with a small library of self-timed...