The objective of this paper is to improve the use of the hardware resources of the trace cache mechanism, reducing the implementation cost with no performance degradation. We achieve that by eliminating the replication of traces between the instruction cache and the trace cache. As we show, the trace cache mechanism is generating a high degree of redundancy between the traces stored in the trac...

It has long been a tenet of the fault-tolerance research community that fault– tolerance is possible by exploiting resource redundancy in order to achieve the mission result. Hardware designers, for instance, rely upon various forms of redundant hardware to ensure the availability of at least one system that can produce correct responses. Strangely, one source of redundancy has not been compreh...

this paper proposes an efficient algorithm based on memetic algorithm (ma) for a redundancy allocation problem without component mixing (rapcm) in a series-parallel system when the redundancy strategy can be chosen for individual subsystems. majority of the solution methods for the general rapcm assume that the type of a redundancy strategy for each subsystem is pre-determined and known a prior...

Hardware redundancy may be used in a variety of manners to achieve fault tolerance. One of the most popular techniques is a triple modular redundancy (TMR) scheme. Such a scheme has also been referred to as masking redundancy because failures those affect only if one of the three modules is masked by the majority of the nonfailed modules. Most of the published works on TMR make one crucial assu...

Redundancy allocation is one of the common techniques to increase the reliability of the bridge systems. Many studies on the general redundancy allocation problems assume that the redundancy strategy for each subsystem is predetermined and fixed. In general, active redundancy has received more attention in the past. However, in real world, a particular system design contains both active and col...

Multiple instruction rollback (MIR) is a technique that has been implemented in mainframe computers to provide rapid recovery from transient processor failures. Hardware-based MIR designs eliminate rollback data hazards by providing data redundancy implemented in hardware. Compilerbased MIR designshave also been developed which remove rollbackdata hazards directlywith data-flowtransformations. ...

Redundant system with three two-degree-of-freedom (2-DOF) inertial sensors is one of the possible candidates for the UAV inertial sensor redundancy management system. In the conventional FDI techniques using hardware redundancy, at least four 2DOF inertial sensors are needed to detect and isolate the faulty sensor. Since two input axes of 2-DOF inertial sensors are mechanically correlated with ...

Mission critical systems typically employ multistring redundancy to cope with possible hardware failure. Such systems are only as fault tolerant as there are many redundant strings. Once a particular critical component exhausts its redundant spares, the multi-string architecture cannot tolerate any further hardware failure. This paper aims at addressing such catastrophic faults through the use ...

Wireless Sensor Networks (WSN) are useful for monitoring of physical conditions and passing the data gathered to the required location. They are like any other system prone to failure due to limitation of resources. In this paper we address fault tolerance concept in general, give analysis to the definition of fault tolerance and terms related to it based on the system requirements. We explored...

In addition to being accurate, it is important that diagnostic systems for use in automobiles also have low development and hardware costs. Model-based methods have shown promise at reducing hardware costs since they use analytical redundancy to reduce physical redundancy. In addition to requiring no extra sensors, the diagnostic system presented in this paper also allows for high accuracy and ...