Designing a Java processor supporting horizontal multithreading has been becoming more attractive as network computing gains importance. Different from the traditional superscalar processors that issue multiple instructions from a single instruction stream to exploit the instruction level parallelism (ILP), the horizontal multithreading Java processors issue multiple instructions (bytecodes) fr...

This paper introduces an efficient hardware approach to reduce the register file energy consumption by turning unused registers into a low power state. Bypassing the register fields of the fetch instruction to the decode stage allows the identification of registers required by the current instruction (instruction predecode) and allows the control logic to turn them back on. They are put into th...

Power consumption has become an increasing concern in high performance microprocessor design in terms of packaging and cooling cost. The fetch unit including instruction cache contributes a large portion of the total power consumption in the microprocessor. The instruction cache itself suffers some hidden power consumption due to dynamic control flows. Although capturing the dynamic control flo...

This dissertation evaluates factors that affect the energy-efficiency of the fetch engine in a programmable uniprocessor. The central thesis is that branch prediction is one of the key factors affecting overall processor energy-efficiency. Cooling costs, extending battery life in mobile devices, and reducing utility costs for wall-powered systems, especially data centers are growing concerns. T...

Statically-scheduled architectures such as very long instruction word (VLIW) architectures use very wide instruction words in conjunction with high bandwidth to the instruction cache to achieve multiple instruction issue. The encoding used for the instructions can have an e ect on the requirements placed on the instruction fetch and instruction cache hardware. One type of encoding is a compress...

A growing number of studies have explored the use of trace caches as a mechanism to increase instruction fetch bandwidth. The trace cache is a memory structure that stores statically non-contiguous but dynamically adjacent instructions in contiguous memory locations. When coupled with an aggressive trace or multiple branch predictor, it can fetch multiple basic blocks per cycle using a single-p...

Minimizing program code size reduces power consumption and space, which is especially important in embedded systems. Existing variable-length instruction formats provide higher code densities than fixed-length formats, but are ill-suited to pipelined or parallel instruction fetch and decode. This thesis presents a new variable-length instruction format that supports parallel fetch and decode of...

In order to overcome the branch execution penalties of hard-to-predict instruction branches, two new instruction fetch micro-architectural methods are proposed in this paper. In addition, to compare performance of the two proposed methods, different instruction fetch policy schemes of existing multi-branch path architectures are evaluated. An improvement in Instructions Per Cycle (IPC) of 29.4%...

Branches interrupt the sequential flow of instructions and introduce pipeline bubbles. Branch penalty can be a significant component of effective cpi (cycles per instruction) in multiple instruction issue processors. Two key issues need to be resolved to alleviate this problem: a branch resolution scheme to decide the direction and target of a branch early in the pipeline, thus allowing target ...

This paper focuses on reducing power in instruction cache by eliminating the fetching of instructions that are not needed from a cache line. We propose a mechanism that predicts which instructions are going to be used out of a cache line before that line is fetched into the instruction buffer. The average instruction cache power savings obtained by using our fetch predictor is 22% for SPEC95 be...