Interconnect parasitics are dominating circuit performance, signal integrity and reliability in IC design. Copper/low-k process effects are becoming increasingly important to accurately model interconnect parasitics. Even if the interconnect process profile is accurately represented, approximations in parasitic extraction could cause large errors. Typically, researchers and designers have been ...

It is rapidly becoming obvious that with the current trends in technology, interconnect delays are becoming an increasingly dominant factor in determining circuit speed. Until recently, interconnect resistance was often insigni cant, while its capacitance was not, and hence optimal interconnect design frequently involved ensuring that all wire sizes were minimal. However, with advancement in te...

Each new semiconductor technology node brings smaller transistors and wires. Although this makes transistors faster, wires get slower. In nano-scale regime, the standard copper (Cu) interconnect will become a major hurdle for FPGA interconnect due to their high resistivity and electromigration. This paper presents the comprehensive evaluation of mixed CNT bundle interconnects and investigates t...

Interconnect tuning is an increasingly critical degree of freedom in the design of high-performance VLSI systems. By interconnect tuning, we refer to the selection by a design team of line thicknesses, widths and spacings in multi-layer interconnect to simultaneously achieve: (i) distribution (available wiring density) for local signals, global signals, clock, power and ground; (ii) performance...

Interconnect tuning and repeater insertion are necessary to optimize interconnectdelay, signalperformance and integrity, and interconnectmanufacturability and reliability. Repeater insertion in interconnects is an increasingly important element in the physicaldesign of high-performance VLSI systems. By interconnect tuning, we refer to the selection of line thicknesses, widths and spacings in mu...

This paper presents a novel approach to interconnect fault location for FPGAs during power-on sequence. The method is based on a concept known as fault grading which utilizes defect knowledge during manufacturing test to classify faulty devices into different defect groups. A Built-In Self-Test (BIST) method that can efficiently identify the exact location of the interconnect fault is introduce...

This paper provides an overview of ULSI interconnect scaling trends and their implications for thermal, reliability and performance issues simultaneously. It shows how interconnect scaling requirements for deep sub-micron (DSM) technologies cause increasing thermal effects. The paper then examines the impact of thermal effects on both interconnect design and electromigration (EM) reliability. S...

The Steiner minimum tree problem, which asks for a minimum-length interconnection of a given set of terminals in the plane, is one of the fundamental problems in Very Large Scale Integration (VLSI) physical design. Although advances in VLSI manufacturing technologies have introduced additional routing objectives, minimum length continues to be the primary objective when routing non-critical net...

Interconnect planning has been widely regarded as one of the most critical factors in determining the system performance and total power consumption as technology scales. Because of shrinking dimension, on-chip wires are getting more resistive, and the wire delay is becoming larger comparing to gate delay. On the other hand, the self capacitance of wires does not scale with feature size, and as...