Reducing test cost by minimizing the overall test time is one of the main goals of System-on-Chip (SoC) test scheduling. Power-aware strategies optimize the overall test time of a test schedule for a global peak power budget. For powerconstrained test scheduling with multiple test clock frequencies, a fast heuristic method for sessionless test scheduling is proposed. Experiments on several ITC’...

As currently practiced, value-added assessment relies on a strong assumption about the scales used to measure student achievement, namely that these are interval scales, with equal-sized gains at all points on the scale representing the same increment of learning. Many of the metrics in which test results are expressed do not have this property (e.g., percentile ranks, normal curve equivalents)...

While technology is changing the face of the world, it itself is changing by leaps and bounds; there is a continuing trend to put more functionality on the same piece of silicon. Without major changes in the CMOS technology, it has been shown that the scaling of devices has signi cant impact on the e ectiveness of Iddq testing. The sensitivity of Iddq testing to individual device parameters is ...

With joint contributions from academia and industry, this special issue provides a balanced overview of the area fiber-optic network capacity scaling.