0-7803-7542-4/02 $17.00 © 2002 IEEE Panel P7.4 ITC INTERNATIONAL TEST CONFERENCE SELECTIVE OPTIMIZATION OF TEST FOR EMBEDDED FLASH MEMORY Roger Barth Intel Corporation The Problem Embedded memory has never been the easiest memory to test since it is generally hidden behind a large amount of intervening circuitry. Over the years, DAT (Direct Access Test) has eased the problem for the test engin...

Historic contexts remind us of an era when cities were built based on the needs, goals, and preferences of their inhabitants. In other words, the mental world of both the builders and the inhabitants was closely interrelated. But by ignoring citizens' memories and interests and their mental needs, today's interventions with rapid developments within historic contexts have led to amnesia and the...

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Embedded memory test and diagnosis is becoming an important issue in system-on-chip (SOC) development. Direct access of the memory cores from the limited number of I/O pins is usually not feasible. Built-in self-diagnosis (BISD), which include built-in self-test (BIST), is rapidly becoming the most acceptable solution. We propose a BISD design and a fault diagnosis system for embedded SRAM. It ...

Memories are the most dominating blocks present on a chip. All types of chips contain embedded memories such as a Read Only Memory (ROM), Static Random Access Memory (SRAM), Dynamic Random Access Memory (DRAM), and flash memory. Testing of these memories is a very tedious and challenging job as area over head, testing time and cost of the test play an important role. In this work an efficient V...

Memories are the most dominating blocks present on a chip. All types of chips contain embedded memories such as a ROM, SRAM, DRAM, and flash memory. Testing of these memories is a very tedious and challenging job as area over head, testing time and cost of the test play an important role. Embedded memories are occupying a significant portion of the System-on-chip area. Because of this trend and...

We test a selection of associative memory models built with different connection strategies, exploring the relationship between the structural properties of each network and its pattern-completion performance. It is found that the Local Efficiency of the network can be used to predict pattern completion performance for associative memory models built with a range of different connection strateg...

We suggest electronic circuits with memristors (resistors with memory) that operate as memcapacitors (capacitors with memory) and meminductors (inductors with memory). Using a memristor emulator, the suggested circuits have been built and their operation has been demonstrated, showing a useful and interesting connection between the three memory elements.