1. Introduction Logic Built-In Self-Test (BIST) schemes based on STUMPS structure use on-chip circuitry to generate test stimuli and analyze test responses, with little or no help from an ATE. The STUMPS (Self-Test Using a MISR and Parallel Shift register sequence generator) structure applies pseudo-random patterns generated by a PRPG (Pseudo-Random Pattern Generator) to a full-scan circuit in ...

Built-in self-test (BIST) is an attractive approach to detect delay faults because of its inherent support for at-speed test. Deterministic logic BIST (DLBIST) is a technique that has been successfully applied to stuck-at fault testing. As delay faults have lower random pattern testability than stuck-at faults, the need for DLBIST schemes has increased. However, an extension to delay fault test...

Introduction In the virtual component (VC) integration business, the embedded DRAM is a key VC to realize high bit density and high bandwidth performance, thus the low-cost testing of DRAM-integrated LSI is an emerged problem. The DRAM test usually includes a fail-bit (address) search to repair the memory cell defects with redundancy, requiring long time for wafer probing. A DRAM BIST drastical...

Reseeding is used to improve fault coverage in pseudo-random testing. Most of the work done on reseeding is based on storing the seeds in an external tester. Besides its high cost, testing using automatic test equipment (ATE) makes it hard to test the circuit while in the system. In this paper, we present a technique for built-in reseeding. Our technique requires no storage for the seeds. The s...

Increasing number of pins or gates in the latest LSI’s requires a lot of testing resources. The conventional scan-based testing requires a costly tester (ATE) equipped with a lot of pin electronics. Since reducing the testing cost is a crucial issue in industry, we have introduced an approach using scan-based logic BIST to solve this problem. The logic BIST has applied to many ASIC design chips...

We present the application of a deterministic logic BIST scheme on state-of-the-art industrial circuits. Experimental results show that complete fault coverage can be achieved for industrial circuits up to 100K gates with 10,000 test patterns, at a total area cost for BIST hardware of typically 5%-15%. It is demonstrated that a tradeoff is possible between test quality, test time, and silicon a...

Diagnosing failing vectors in a Built-In Self Test (BIST) environment is a difficult task because of the highly compressed signature coming out of the Multiple Input Shift Register (MISR). The root cause of the failure must be initially narrowed down to the failing vectors and also the scan cells at which mismatches occurred. In this work, we propose a method for accurately determining the firs...

In today’s Integrated Circuits (IC’s) designs Built-in Self Test (BIST) is becoming important for the memory which is the most necessary part of the System on Chip. The March algorithm has been widely used to test memory core of System on chip (SOC). LFSRs and counters are mainly used to generate the memory addresses, which can be serially applied to the memory cores under test. In this paper A...

The generation of significant power droop (PD) during at-speed test performed by Logic BIST is a serious concern for modern ICs. In fact, the PD originated during test may delay signal transitions of the circuit under test (CUT): an effect that may be erroneously recognized as delay faults, with consequent erroneous generation of test fails, and increase in yield loss. In this paper, we propose...