MOSFETs with heavily doped regions at one or both ends of the channel exhibit qualitative differences in electrical behavior compared to devices with laterally uniform channel doping. These differences include a distinct peakiness in the transconductance near threshold, asymmetries in capacitances, and a surprising decrease in the statistical variation of the peak gain factor as channel length ...

Silicon on insulator (SOI) CMOS offers performance gain over bulk CMOS mainly due to reduced parasitic capacitances and latchup. It is most promising technology when low cost low power and low voltage suppply is required. kink effect and self heating are two important points of concern in case of SOI MOSFET. In this paper we first briefly discuss the SOI technology, kink effect and lattice heat...

In this paper, we compare a new 1.2 kV rated 4H-SiC split-gate (SG) MOSFET with the conventional planar-gate (PG) MOSFETs. Both structures were fabricated same design rules and process platform. Therefore, have similar electrical parameters, such as ON-state drain-source resistance (RON), breakdown voltage (BV), threshold (Vth), body diode forward (VSD). It is shown that Ciss/Coss/Crss capacita...

Polyvinilidene fluoride (PVDF) single-element transducers for high-frequency (>30 MHz) ultrasound imaging applications have been developed using MEMS (Micro-electro-Mechanical Systems) compatible techniques. Performance of these transducers has been investigated by analyzing the sources and effects of on-chip parasitic capacitances on the insertion-loss of the transducers. Modeling and experime...

We have fabricated and demonstrated a new device called the vertical replacement-gate (VRG) MOSFET. This is the first MOSFET ever built in which: (1) all critical transistor dimensions are controlled precisely without lithography and dry etch, (2) the gate length is defined by a deposited film thickness, independently of lithography and etch, and (3) a high-quality gate oxide is grown on a sing...

The phase shift full bridge (PSFB) converter allows high efficiency power conversion at high frequencies through zero voltage switching (ZVS); the parasitic drain-to-source capacitance of the MOSFET is discharged by a resonant inductance before the switch is gated resulting in near zero turn-on switching losses. Typically, an extra inductance is added to the leakage inductance of a transformer ...

Continued research into the development of III–V high-electron mobility transistors (HEMTs), specifically the minimization of the device gate length, has yielded the fastest performance reported for any three terminal devices to date. In addition, more recent research has begun to focus on reducing the parasitic device elements such as access resistance and gate fringing capacitance, which beco...

We present a simple, high-sensitivity, array-based capacitive sensor for biological applications. The circuit can accurately sense ungrounded coupling capacitances, while strongly attenuating the effect of unwanted parasitics. It can also perform capacitance-voltage profiling of nonlinear biological capacitances at very low voltages. We implement a dual input frequency ∆Σ modulator to perform i...

This paper focuses on the role of the power MOSFET in achieving high-efficiency converter design. It provides a brief overview of current low-voltage MOSFET trench technologies, along with a discussion about onresistance versus gate charge trade-offs for MOSFETs optimized for use as control or synchronous switches. It covers the importance of the integrated Schottky diode (SyncFETTM MOSFET) in ...

Employment of the <100> channel direction in a strained-Si0.8Ge0.2 p-MOSFET provides a hole mobility enhancement as large as 25% and a parasitic resistance reduction of 20% compared to a <110> strained-Si0.8Ge0.2 channel p-MOSFET, which already has a better mobility and threshold voltage roll-off than the Si p-MOSFET. These results suggest that the <100> strained-SiGe-channel p-MOSFET can be us...