A p a r a l l e l processing method of r o t a t i n g and comparing three-dimensional ob jec ts is presented. The mul t i -p rocessor has an abs t rac t s t ruc tu re in which the I n d i v i d u a l processors are located at the ve r t i ces of a geodesic dome. The design has been tested on the same type of ob ject matching problems as Shepard (3) used in h i s mental r o t a t i o n experime...

Techniques for library-centric application design have already proven to be very useful in the past. The current gain in computer performance is shifted towards the utilisation of multi-core processors which extends the importance of this type of application design in the field of scientific computing, which also poses new difficulties. A parallel generic scientific simulation environment has b...

This paper proposes and evaluates APIs for Inter-Core Time Aggregation Scheduler (IAS), which is a kernel-level thread scheduler to enhance performances of multi-threaded programs on multi-core processors. We have proposed IAS, which is a combination of time-multiplexing and space-multiplexing scheduling to utilize caches existing per processing core and shared between processing cores. We pres...

Optical wavefront interferometry has evolved into increasingly compact and portable forms with optimizations and novel developments from multi-component, bulk-optic configurations to miniaturized multi-core fiber forms; each presents its own advantages, challenges and opportunities. OCIS codes: 030.0030 Coherence; 070.0070 Fourier optics and signal processing; 120.0120 Instrumentation, measurem...

Our main aim of research is to find the limit of Amdahl's Law for multicore processors, to make number of cores giving more efficiency to overall architecture of the CMP(Chip Multi Processor a.k.a. Multicore Processor). As it is expected this limit will be in the architecture of Multicore Processor, or in the programming. We surveyed the architecture of the Multicore processors of various chip ...

On modern multicore processors, many applications run much slower than one would expect when looking at the vast congregated computational power. After a discussion of factors determining the performance on such CPUs, a framework concept that simplifies writing performance-optimized codes for stencil-based algorithms and a prototypical implementation are presented. Finally, the suitability of t...

A Cray XT5 system has recently been installed at Oak Ridge National Laboratory (ORNL). This system differs from the existing XT4 system at ORNL in its compute node architecture, utilizing two quad-core Opteron Barcelona processors instead of a single quad-core Opteron Budapest processor. It also differs in its sheer scale, having approximately 150,000 processor cores, almost 5 times as many as

This paper presents a novel method that improves the efficiency of high-quality surface reconstructions for particle-based fluids using Marching Cubes. By constructing the scalar field only in a narrow band around the surface, the computational complexity and the memory consumption scale with the fluid surface instead of the volume. Furthermore, a parallel implementation of the method is propos...

We compare old single-core multi-processor systems against multi-core processors and study the question which improvements are most relevant for increasing the performance on stencil computations. Even before the multi-core era began, the bandwidth wall, the discrepancy between off-chip bandwidth requirements and system bandwidth performance, was already a significant problem. Because of the cu...

Space systems are hard real-time systems, where the worst-case execution time (WCET) of tasks needs to be known to prove absence of deadline misses. For simple processor and memory architectures it is possible to statically derive a safe upper bound of the WCET. However, future requirements in more autonomous missions require more processing power. This increase in processing power is approache...