Future integrated circuits that contain more than one billion transistors will allow much more complex designs than possible today. Unfortunately, there will be problems with clock distribution and on-chip communication delays. One approach to address these problems is to make a Network on Chip (NoC), that handles communication over the chip. Research in the area is being done at KTH, and a sim...

Modern System-on-Chip (SoC) platforms typically consist of multiple processors and a communication interconnect between them. Network-on-Chip (NoC) arises as a solution to interconnect these systems, which provides a scalable, reusable, and an efficient interconnect. For these SoC platforms, multicast communication is significantly used for parallel applications. Cache coherency in distributed ...

In this paper, we address the problem of high-level exploration of Network-on-Chip (NoC) architectures to early evaluate power/performance trade-offs. The main goal of this work is to propose a methodology supported by a design framework (namely, PIRATE) to generate and to simulate a configurable NoC–IP core for the power/performance exploration of the on-chip interconnection network. The NoC–I...

© 2009 Chia-Ming Wu et al. 111 Network-on-chip (NoC) architecture provides a highperformance communication infrastructure for systemon-chip designs. Circuit-switched networks guarantee transmission latency and throughput; hence, they are suitable for NoC architecture with real-time traffic. In this paper, we propose an efficient integrated scheme which automatically maps application tasks onto ...

Network on Chip (NoC) is a new paradigm for designing large and complex systems on chips (SoCs). In this paradigm, a packet switched network is provided for on-chip communication among cores. NoC paradigm provides the required scalability and reusability to reduce design time of SoCs. A NoC simulator is an important tool required to support development of designs based on a NoC architecture. In...

Network-on-Chip (NOC) has been proposed as an attractive alternative to traditional dedicated wire to achieve high performance and modularity. Power efficiency is the most important concern in NOC design. Routing algorithms have major effect on power and performance. We have implemented an accurate meshbased hardware model for NOC with VHDL and using it, have measured the performance and power ...

The rapid development of Network-on-Chip (NoC) calls for a systematic approach to evaluate and fairly compare various NoC architectures. In this specification, we define a generic NoC architecture, a comprehensive set of synthetic workloads as micro-benchmarks, workload scenarios and evaluation criteria. These micro-benchmarks enable to measure and pinpoint particular properties of NoC architec...

This paper presents efficient methods for online fault detection and diagnosis of Network-on-Chip (NoC) switches. The fault model considered in this research is a system level fault model based on the generic properties of NoC switch functionality. The proposed method is evaluated by fault simulation in a platform using this system level fault model. The experimental results show that with a re...

This paper presents design trade-off and performance impacts of the amount of pipeline phase of control path signals in a wormhole-switched network-on-chip (NoC). The numbers of the pipeline phase of the control path vary between twoand one-cycle pipeline phase. The control paths consist of the routing request paths for output selection and the arbitration paths for input selection. Data commun...

The emerging platform-based design paradigm poses enormous challenges to conceptualizing, implementing, verifying and programming today‟s complex System on Chip (SoC) design. Network-on-Chip (NoC) architecture provides a scalable, high performance and robust infrastructure for on-chip communication. Perfect Difference Network (PDN) based on the mathematical notion of Perfect Difference Set as a...