The design of appropriate communication architectures for complex Systems-on-Chip (SoC) is a challenging task. One promising alternative to solve these problems are Networks-on-Chip (NoCs). Recently, the application of deterministic and stochastic Petri-Nets (DSPNs) to model on-chip communication has been proven to be an attractive method to evaluate and explore different communication aspects....

With more and more processor cores integrated on a chip, Networks-on-chip (NoC) is emerging as a candidate architecture for multiprocessor systems-on-chip (MPSoC). Traditional metallic interconnects have become the bottleneck of NoC due to the limited bandwidth, long delay, and high power consumption. Optical Network-on-Chip (ONoC) can decrease interconnect delay and provide higher bandwidth wi...

Network-on-chip architectures can improve the scalability, performance, and power efficiency of general multiprocessor systems and application-specific heterogeneous multicore and many-core SoCs (MCSoCs). This interconnection paradigm when combined with 3D integration technology offers advantages over 2D NoC design, such as shorter wire length, higher packing density, and smaller footprint. How...

Systems-on-Chip architecture integrates several heterogeneous components on a single chip. A key challenge is to design the communication between the different entities of a SoC in order to minimize the communication overhead. Network-on-chip (NoC) is a new approach for communication infrastructure of Systems-on-Chip (SoC) design, which provides network based solution for on-chip communication....

Networks on Chips (NoCs) are required to tackle the increasing delay and poor scalability issues of bus-based communication architectures. Many of today’s NoC designs are based on single path routing. By utilizing multiple paths for routing, congestion in the network is reduced significantly, which translates to improved network performance or reduced network bandwidth requirements and power co...

Heat balance is of critical importance on the design of network-on-chip (NoC). In a 3D topology NoC, routing algorithm should take considerations of each layer’s peak temperature and traffic to prolong chip’s service life. In this paper, we propose a heat-balanced, deadlock-free routing algorithm named Direct Ratio Transport Layer (DRTL). DRTL distributes and arranges traffics according to the ...

To allow fast communication—at several Gb/s—of multimedia content among processors and memories in a multi-processor system-on-chip, a new approach is emerging in literature: Wireless Network-on-Chip (WiNoC). With reference to this scenario, this paper presents the design of the key element of the WiNoC: the antenna. Specifically, a bow-tie antenna is proposed, which operates at mm-waves and ca...

Network-on-Chip (NoC) has recently emerged as an efficient communication solution for the System-on-Chip (SoC) design. Design space exploration and performance evaluation are the most essential task in NoC design. In this paper, an ABC based design space exploration framework for the NoC design is proposed. The objective of the design space exploration is to minimize the total energy consumptio...