We present a new unified analytical front surface potential model. It is valid in all regions of operation (from the sub-threshold to the strong inversion) and an analytical expression for the critical voltage Vc delineating the partially depleted (PD) and the fully depleted (FD) region is introduced. The drift/diffusion equation is used to derive a single formula for the drain current valid in...

The dual supply voltage (dual-VDD) scheme reduces the active power consumption without performance degradation by using two power supply rails. However, an increase in the delay due to the scaled-down supply voltage has made assigning the lower supply voltage (VDDL) more difficult in the conventional dual-VDD scheme. We propose a technique for the dual-VDD scheme employing the Active Body-biasi...

This work presents an Improved Charge Sheet compact Model (ICSM) especially valuable for distortion analysis, where precise calculation of derivatives of at least third order is required. A new expression for the charge is used in the calculation of the current. Vertical electric field, mobility and DIBL are represented using previously reported for other purposes more precise expressions. The ...

Instability of SRAM memory cells derived from aggressive technology scaling has been recently one of the most significant issues. Although a 7T-SRAM cell with an area-tolerable separated read port improves read margins even at sub-1V, it unfortunately results in degradation of write margins. In order to assist the write operation, we address a new memory cell employing a look-ahead body-bias wh...

Silicon-on-insulator (SOI) CMOS offers a 20–35% performance gain over bulk CMOS. High-performance microprocessors using SOI CMOS have been commercially available since 1998. As the technology moves to the 0.13m generation, SOI is being used by more companies, and its application is spreading to lower-end microprocessors and SRAMs. In this paper, after giving a short history of SOI in IBM, we de...

Silicon On Insulator (SOI) can leverage a lot of new advantages for circuit designers compared to conventional bulk technology. In particular, the improved S-factor and reduced junction capacitance make it very appealing for next generation low power, high performance DRAM systems. However, the benefits of the SOI technology do not come entirely for free. In this project, we characterized the k...

This letter investigates hot-carrier-induced degradation on 0.1 m partially depleted silicon-on-insulator (SOI) nMOSFETs at various ambient temperatures. The thermal impact on device degradation was investigated with respect to body-contact nMOSFETs (BC-SOI) and floating-body SOI nMOSFETs (FB-SOI). Experimental results show that hot-carrier-induced degradation on drive capacity of FB-SOI device...

Superconductors comprising 5d transition metals of Ir and Pt have been widely explored because they the potential unique superconductivity caused by strong spin-orbit interaction (SOI). We successfully synthesized BaIr2, last Laves phase remaining unsynthesized in MgCu2-type AM2 (A = Ca, Sr, Ba; M Rh, Pd, Ir, Pt). BaIr2 was crystallized at 925 C under a pressure 3.3 GPa via solid-state reaction...